IEEE Solid-State Circuits Magazine - Fall 2015 - 24
|G-1(f )|
|G(f )|
Transmitter
Output
Receiver
Input
Equalizer
Output
f
f0
f0
f1
f2
f
Linear Equalizer
Channel
Figure 1: The basic concept of linear equalization.
A decision feedback equalizer is able to
compensate for ISI without amplifying
noise or crosstalk.
RL
RL
Vout
gm
Vin
Rd
Cd
Figure 2: A zero-peaked differential
amplifier.
once noise is considered). In practice, maintaining accurate compensation of the channel up to a finite
bandwidth (f1) equal to 0.7 of the bit
(baud) rate, say, yields a clean output signal with acceptable rise/fall
times (as indicated by the red eye
diagram in the figure).
A linear equalizer can be further
classified according to the nature
of its transfer function. In a continuous-time linear equalizer (CTLE),
the transfer function is defined by
simple S-domain poles and zeros. In
particular, if one or more real zeros
are placed below the frequency of
any pole (e.g., at f0 in Figure 1), the
transfer function provides highfrequency peaking that helps compensate the channel loss. While
such a characteristic is sometimes
obtained with just a high-pass RC
filter, a passive equalizer provides
only de-emphasis, attenuating the
low-frequency components of the
signal rather than amplifying the
high-frequency components. When
R1B
R1A
gm1B
Gain
Stage
R2
Cc
Vin
gm1A
gm2
Input Stages
gmFB
Figure 3: A peaking amplifier with an active feedback structure.
24
fa l l 2 0 15
IEEE SOLID-STATE CIRCUITS MAGAZINE
Vout
the channel losses are high (e.g.,
>20 dB), high-frequency gain is
needed to enhance receiver sensitivity, so today most CTLEs are
active circuits known as peaking amplifiers. The most common
peaking amplifier is the zeropeaked differential amplifier with
RC source degeneration, shown in
Figure 2. The degeneration resistance R d can be chosen so that the
dc gain of the amplifier is about
unity. At high frequencies, capacitor C d begins to short out R d , and
the gain rises. The amount of peaking achieved at a given frequency
depends on the position of the
zero, which can be tuned by switching the value of C d . Note, however,
that the high-frequency gain of this
topology cannot exceed the dc gain
of a nondegenerated current-mode
logic (CML) stage, equal to gmR L,
where gm is the transconductance
of the differential pair transistors.
When the desired level of peaking
exceeds 4-6 dB, alternative circuit
structures providing more high-frequency gain are favored. Figure 3
shows one such structure [1], which
employs capacitively coupled parallel input stages and active feedback. (A single-ended representation is used in the figure to avoid
clutter. Each transconductance stage
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015
IEEE Solid-State Circuits Magazine - Fall 2015 - Cover1
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