IEEE Solid-State Circuits Magazine - Fall 2015 - 27

propagation. If the decision-making
slicer makes an error, the feedback
signals will be corrupted, so incorrect ISI compensation will be applied
to future data bits. Therefore, the
error rate may be temporarily elevated (until a string of good data
decisions fills up the shift register).
While the overall bit-error rate (BER)
of the DFE may be low, its tendency
to produce bursts of errors motivates the use of forward error correction codes such as Reed-Solomon
codes, which are well suited to correcting such bursts [14].
A key challenge in designing a
high-speed DFE is ensuring that
the feedback signals are accurately
established at the slicer input by the
time the data decision is made. The
critical path, marked with a dashed
red line in Figure 5, is the H1 (first
tap) feedback loop, whose delay
must be lower than 1 UI. Meeting this
timing constraint becomes difficult
at data rates above 20 Gb/s. The timing constraint on the H1 feedback
path can be relaxed by adopting a
technique known as speculation or
loop unrolling [15]. Figure 7 presents the block diagram of a half-rate
DFE employing one tap of speculation. The upper DFE half detects
the even data bits, and the lower
DFE half detects the odd data bits.
Within each half, both +H1 and -H1
are added as dc offsets to the data
input with parallel analog summers,
whose outputs are sliced to binary
values. (Ignore for the moment the
eye monitoring path at the bottom of
the figure; its use will be discussed
in the following paragraph.) Since
the previous data bit can have only
one of two values, one of these parallel paths represents the correct
polarity of H1 compensation. Once
the previous data bit is known, the
correct slicer output is selected with
a MUX. With the H1 tap realized by
speculation, the H2 feedback loop
becomes the critical timing path,
whose delay must be lower than 2
UI. Additional DFE taps may be speculated to achieve even higher speed
operation but at a significant cost in

hardware, as the number of parallel
slicing paths grows exponentially
(2 s) with the number (S) of speculative taps. The largest number of
speculative taps reported to date is
three, which was used in implementing a 30-Gb/s 15-tap DFE [16].
The eye-monitoring path at the
bottom of Figure 7 provides information that is used to adapt the DFE tap
coefficients. A programmable offset is
added to the data signal so that the
top (or bottom) of the equalized eye

Hi n + 1 = Hi n - d $ Amp n $ D n - i,
where n is the time index, Amp and
D are treated as binary values (±1),
and d is a small number that sets the
speed of convergence. Consider, for
instance, the H2 coefficient (i = 2) .
If the Amp sample is usually positive
when the D bit 2 UI earlier is 1 and
usually negative when the D bit 2 UI
earlier is -1, a positive correlation
will be detected, and the logic will
slowly make the H2 tap coefficient

Devising CTLE topologies with improved
high-frequency peaking remains an active
area of study.
is compared with an expected target.
The resulting error samples (Amp)
and the DFE output data are delivered
to the adaptation logic, where the sign
errors of the Amp samples are correlated with the polarities of various
data bits. Since only the signs (not the
magnitudes) are correlated, the adaptive algorithm is known as sign-sign
LMS [17], with the updates to the i th
tap coefficient (Hi) given by

Deven

Σ
+H1

more negative to reduce the residual
ISI. After convergence of the DFE
adaptation, the Amp sample is uncorrelated with the bit 2 UI earlier.
A critical circuit affecting the performance and power efficiency of
a DFE is its summer, which needs to
add the DFE feedback signals to the
data input with small delay. Earlier
DFEs [18] employed the resistively
loaded CML summer shown in Figure 8.

C2
C2

C2
L

-H1
Data
Input

Σ
C2

H2-H5

Tap Feedback
and Weighting

Σ
+H1

-H1
C2

L
C2

Offset

C2
Dodd

Amp
C2

Figure 7: A half-rate DFE architecture with speculative first (H1) tap. The dashed red line
shows a new critical timing path.

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015