IEEE Solid-State Circuits Magazine - Fall 2015 - 29

CLK
INTOUTP

CL

INTOUTN
INP

CLK

CHi

CHi

INN

CL

Integrate

Integrate

Reset

INTOUTP
INTOUTN
HiP

HiN
IB

Sample

AVDD
(a)

Reset

DFE Taps

xM

(b)

Sample
Hi Tap
Applied Here

Figure 10: A current-integrating summer with switched-capacitor feedback replacing current feedback.

The power and effectiveness of these
equalization techniques are now
illustrated by presenting some of the
measurement results obtained with
the 28-Gb/s transceiver described in
[1]. Implemented in 32-nm SOI CMOS
technology, that transceiver employs
many of the equalizer circuits discussed in this article. The transmitter includes a 4-tap baud-spaced FFE,
and the receiver includes a two-stage
CTLE (peaking amplifier) and a 15-tap
DFE based on current-integrating
summers. The first stage of the CTLE
employs the active feedback structure of Figure 3, while its second
stage is based on the zero-peaked
differential amplifier of Figure 2.
The receiver architecture allows the
clock phase of the internal eye monitor to be swept independently with
respect to the data sampling clock.
This permits the eye monitor to be
used as an on-chip sampling oscilloscope for repetitive data patterns.
For instance, measurements of the
receiver's response to an isolated
"one" bit at 28 Gb/s show that the
analog data path provides close to
10 dB of peaking at 14 GHz when
the CTLE is configured for maximum
high-frequency boost [1].
The internal eye monitor can
also be used to measure the equalized eye of the receiver (i.e., after
DFE taps are applied). One such

measurement at 25 Gb/s is shown
in Figure 11. S-parameter measurements of the channel show a loss
of 33 dB at 12.5 GHz (half-baud frequency). The S-parameter measurements do not include the losses of
the transmitter and receiver packages, however. Accounting for the
package losses, the total loss is
about 38 dB. Without equalization,
such high losses would completely
shut down the eye diagram. (To put
this in perspective, a 1010 pattern
is attenuated by almost two orders
of magnitude!) With application of
both linear and DFE equalization, an

open eye diagram with healthy margins is obtained. The vertical scale in
Figure 11 is marked in least-significant bits (LSBs) of an on-chip DAC.
With an LSB value of about 2.5 mV,
the vertical eye opening exceeds
150 mV (peak-to-peak differential).
The data processing with the
internal eye monitor is too slow
to measure receiver performance
at very low BERs. Instead, the bit
errors are measured with a BER tester (BERT). The performance is summarized in a bathtub curve, in which
the measured BER is plotted against
the data sampling position (adjusted

100

Amplitude (LSBs)

Equalization Examples

50

0

-50

-100
-1/2

-1/4

0
Time (UI)

1/4

Figure 11: The measured internal eye of a receiver demonstrating equalization of a 38-dB
loss channel at 25 Gb/s.

IEEE SOLID-STATE CIRCUITS MAGAZINE

fa l l 2 0 15

29



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015

IEEE Solid-State Circuits Magazine - Fall 2015 - Cover1
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IEEE Solid-State Circuits Magazine - Fall 2015 - 1
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