IEEE Solid-State Circuits Magazine - Fall 2015 - 30

Future Directions

with a clock phase rotator). Figure 12
presents the results of a 28-Gb/s
equalization experiment with a test
channel comprising a 15-in PCB
trace, 3.7 in of evaluation card traces,
and interconnect cables. S-parameter
measurements [Figure 12(a)] show
a channel loss of 29 dB at 14 GHz,
with the transmitter and receiver
package losses bringing the total to
35 dB. Figure 12(b) shows the equalized bathtub curve with a 28-Gb/s
PRBS31 data pattern. The horizontal

While analog and mixed-signal
equalizer circuits will continue to
evolve and improve, a paradigm
shift in electrical link equalization
is on the horizon with the advent
of the analog-to-digital converter
(ADC)-based receiver, whose basic
concept is illustrated in Figure 13.
The ADC digitizes the data input
with modest resolution (e.g., 5
or 6 bits), and the equalization
is performed with digital signal

The equalization capabilities of transceivers
continue to improve.

processing (DSP). Placing a linear
equalizer in front of the ADC is optional but often useful in reducing
the resolution requirements of the
ADC and the digital processing circuits [21]. There are important advantages to performing most of the
equalization in the digital domain.
Digital implementation enhances
portability to different technology
nodes and improves testability.

eye opening is 35.6% of UI at a BER
of 10 -9, which provides good timing margin for the CDR. Operation is
error free (BER < 10 -13) at eye center.
It is worth noting that the equalization capabilities of transceivers continue to improve. Earlier this year a
backplane transceiver was reported
[11] that successfully equalizes a
channel with 40 dB of loss (not even
counting the package losses!).

0
-20
BER

S21 (dB)

10-6

-29 dB at 14 GHz

-10
-30
-40
-50
-60

10-8

35.6% at 10-9

10-10
10-12

10 15 20 25
Frequency (GHz)
(a)

-12 -8

-4 0
4
8
Rotator Position
(b)

Figure 12: An equalization experiment with a test channel including 15-in trace on a PCB:
(a) S-parameters of a 15-in PCB trace, interconnect cables, and evaluation card and (b) an
equalized bathtub curve with a 28-Gb/s PRBS31 data pattern.

Receiver
Input

Optional
Linear EQ

ADC

Figure 13: An ADC-based I/O receiver.

fa l l 2 0 15

IEEE SOLID-STATE CIRCUITS MAGAZINE

Digital EQ

Data

ADC-based receivers are also compatible with more complex modulation schemes such as multilevel
pulse-amplitude modulation, and
DSP enables the implementation
of more sophisticated detection
schemes such as Viterbi decoding
(even more powerful than DFE, another potential "game changer" if a
practical implementation is found).
Such advanced modulation and
detection schemes will eventually
become necessary with the push
to higher data rates (due to higher
channel losses) and indeed are already being considered for upcoming 56 Gb/s standards.
In fact, a backplane transceiver
using a baud-rate ADC was successfully demonstrated several years
ago at a data rate of 12.5 Gb/s [22].
A two-tap FFE and a five-tap DFE
were implemented in the digital
domain. The power consumption
of the high-speed ADC and DSP circuits put such a solution at a competitive disadvantage, though, and
mixed-signal equalization is still
the dominant approach today in
a world of power-constrained I/O.
However, the power efficiency gap
is expected to close with continued
technology scaling, which benefits
digital circuits more than analog
ones. Indeed significant progress
has been recently reported in this
direction. A 6-bit ADC has been
shown [23] to operate at a sampling
rate of 36 GS/s with only 110 mW
of power dissipation, which would
translate to an energy efficiency
of 3.1 pJ/bit when used in an I/O
receiver. A low-power DSP design
for a 16-Gb/s backplane I/O is
described in [24]. The DSP equalizer features an eight-tap FFE and
a "4+4"-tap DFE, which is so named
because the operational DFE taps
are H1-H4 and H9-H12. The latency
of a digital adder circuit prevents
efficient implementation of DFE
taps H5-H8; ISI in that time span
is compensated instead by the FFE.
An FFE contains no feedback loops,
so its digital design can be easily parallelized for relaxed timing

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015