IEEE Solid-State Circuits Magazine - Fall 2015 - 34

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Figure 2: N-cycle jitter representation.

Clock Synthesis
The generation of a clock for a local
domain is a task important to many
electronic systems, but it is especially
critical for high-speed signaling systems. One reason clock quality is so
important for high-speed links is that
wireline frequencies are normally
much greater than the on-chip datapath frequencies. Links require much
higher per-lane throughput than the
typical data-path circuit because
minimizing the number of package
pins and board traces is important
for optimizing the overall system
cost. Additionally, clocks not only
need to be precise and consistent for
high-speed logic circuit performance;
clock quality is even more important to reduce destructive distortion
effects on the link output waveform.
Figure 1 demonstrates the critical
nature of clock quality and precise
edge placement on high-speed link
transmit waveforms. Specifically, a
phenomena known as jitter (generally defined as a nonideality or uncertainty in the edge placement of
a clock waveform) results in distortion of the signaling waveforms due
to the edge placement being shifted
from the ideal location. This, in turn,
results in the amplification of intersymbol interference (ISI). Normally,
ISI resulting from channel loss can
be mitigated by using equalization
to correct the symbols back to their
desired shape. However, edge placement uncertainty due to jitter is normally unpredictable, and the amplified ISI is not alleviated effectively
by most equalization circuits.
Because clock quality is a paramount concern when designing
for interoperability, clock and jitter metrics and terminology are at
the foundation of many industry

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standard link specifications. Additionally, to optimize the performance of aggressive high-speed
data links, it is crucial that designers and system architects understand jitter terminology and metrics
as well as comprehend the sources
and origin of jitter and its related
consequences.

Oscillator Phase Noise
One of the most basic systems central
to clock synthesis techniques is an
oscillator. Ideally, an oscillator vibrates
at a fixed frequency due to a dominant
positive feedback mechanism isolated
to a single frequency. However, fundamental interference sources, such as
thermal and flicker noise, randomly
disturb normal circuit operation and
cause voltage-induced timing noise,
which subsequently results in oscillator phase deviation from ideal.
For example, an oscillator may
experience a phase shift due to voltage
noise within the circuit. Depending
on the timing of the noise spike with
respect to the oscillation waveform,
the output phase will shift accordingly.
In the example oscillator, noise spikes
that align with the peak of the oscillation waveforms may experience very
little phase perturbation, while noise
spikes injected at the oscillator zerocrossing may result in large phase
shifts. The sensitivity of the noise
impulse phase on the output phaseshift error is characterized by the
impulse sensitivity function (ISF) [2].
Methods for reducing oscillator
phase error are usually focused on
either reducing the magnitude of
the ISF or attempting to attenuate
the internal oscillator noise. For
example, reducing the ISF may be
accomplished by utilizing a resonant oscillator, which effectively

IEEE SOLID-STATE CIRCUITS MAGAZINE

filters noise beyond the operating
frequency. Alternatively, reducing
the effect of oscillator noise requires
enhancing the signal-to-noise ratio,
which may be achieved by increasing the power of the design.
A shift in an open-loop oscillator
phase due to a single noise event will
result in the same magnitude of longterm phase displacement. This phase
noise accumulation effect is a result
of the phase-integrating nature of an
oscillator. Given that thermal noise is
normally distributed, the phase error
on the output of a thermal-noisedominated oscillator will exhibit jitter
accumulation. In this case, the standard deviation of the jitter is proportional to the square root of the time
allowed to accumulate, as illustrated
in the clock waveform of Figure 2.
An alternative representation of
oscillator jitter accumulation due to
thermal noise is shown in Figure 3,
with the magnitude of jitter as a function of accumulation cycles, often
referred to as N-cycle jitter. Due to
the square-root relationship between
jitter and accumulation time, the
slope of the jitter accumulation characteristic is a line with a slope of 1/2
on a dual-logarithmic scale.

Phase-Locked Loop Architectures
To mitigate the amount of oscillator
jitter accumulation, it is common to
utilize a reference clock combined
with a control loop to stabilize both
phase and frequency, resulting in a
phase-locked loop (PLL) architecture.
Additionally, PLLs are used not only
to stabilize clock phase but also to
enable clock multiplication with
a subrate reference clock source,
based on the general representation
of a PLL architecture in Figure 4.
Figure 3 demonstrates the impact
of PLL compensation using an ideal
reference clock by dampening the
long-term phase error of the internal
oscillator. Therefore, the PLL operates
as a high-pass phase filter (up to the
loop bandwidth of the phase-control
loop.) Conversely, a PLL attenuates
high-frequency reference clock jitter
but allows low-frequency reference

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015