IEEE Solid-State Circuits Magazine - Fall 2015 - 36

variation of clock circuits. Many integrated circuits incorporate both a
high-speed interface and a clocking
circuit, as well as very large digital
systems that generate a significant
amount of supply noise at the chip
and system level.
Additionally, modern systems are
aggressively incorporating more power

actively manage the power state of the
link and clocking circuits. In this case,
maintaining precise clocks generated
from a circuit with a settling supply
can be a significant challenge. Because
of this, supply noise mitigation, such
as supply domain isolation and passive or active filtering techniques,
helps protect the most sensitive clock

Because clock quality is a paramount concern
when designing for interoperability,
clock and jitter metrics and terminology
are at the foundation of many
industry standard link specifications.
management techniques by enabling
the active circuit blocks only when
they are needed. This results in large
power supply current changes per
given time unit and subsequently
causes greater voltage rail noise.
However, these supply noise mitigation techniques often result in either
a power or cost penalty and are frequently applied only to those circuits
that need it the most.
Compounding the supply noise
problem is the architectural push to

(a)

Normalized
Jitter

(b)

Edge Nubmer
(c)

Figure 6: The normalized jitter impulse
response of a bandwidth-limited circuit.
(a) The ideal input clock wave form superimposed with the clock incorporating jitter
impulse stimulus. (b) The output clock waveforms using ideal clock versus jitter impulse
clock. (c) The jitter impulse response.

fa l l 2 0 15

supplies. Furthermore, architectural
coordination of power states between
different blocks can dramatically
improve the behavior of supply noise.
Most, if not all, of these techniques
are presently in common use and will
likely be used more broadly and with
finer granularity in the future.

Clock Distribution
Since clock synthesis can be quite
costly in terms of power, area, and
complexity, synthesizing clocks in a
centralized manner and then distributing to multiple receiving points is
often the most efficient approach.
However, given that wireline circuit
clock frequencies can be exceedingly
high (as high as 10-20 GHz is not uncommon) and link performance can
be very susceptible to jitter, care must
be taken in the clock distribution design to avoid harmful jitter effects.
A common clock distribution topology consists of a clock synthesized from a centralized PLL and
then sent to a series of transmitter
circuits in a port arrangement. It is
typical to share many transmitters
multiple mm away from a common
PLL source (and it is not unheard of
to have 32 or more transmitters leverage the same source). Not only
does this shared clock topology have
the advantage of optimized area, but
much of the lower frequency jitter

IEEE SOLID-STATE CIRCUITS MAGAZINE

added by the clock synthesis and
distribution will be highly correlated
at the transmitters. This provides
performance benefits for certain parallel clock recovery topologies that
can take advantage of correlated jitter between neighboring lanes. Additionally, parallel receiver topologies
can also often benefit from a centralized clock distribution approach to
reduce both area and power versus
a dedicated synthesis circuits on a
per-lane basis.
A conventional clock distribution
scheme consists of a series of active
buffers as well as a metal interconnect. Using this approach, accumulation of jitter is not a concern as it is
in the PLL design due to the lack of
a phase-integration mechanism like
an oscillator. However, given that
the delay of clock buffers modulates
with supply level, supply noise adds
jitter to the output waveform. As in
the case of clock synthesis, regulators and other supply noise filtering
can be employed to reduce the noise
experienced by the buffers. However, because clock distribution can
span large distances, it can be very
challenging to dedicate a regulated
low-noise supply for distribution
purposes, and difficult tradeoffs are
usually made to co-optimize clock
distribution power, cost, and area.

Jitter Amplification
A detrimental effect of some clock
distribution designs is jitter amplification, which can be caused by insufficient analog bandwidth of the
network. An intuitive explanation for
jitter amplification may be helpful to
understand the theoretical basis for
what causes this effect.
An impulse response of a loworder low pass filter is an attenuated
pulse with a long tail. Although clock
networks are often nonlinear and are
not usually conducive to linear timeinvariant (LTI) analysis, it is helpful
to extend LTI relationships to the
clock distribution problem. Applying this same principle to the clock
waveforms of Figure 6, note that
with an ideal trapezoidal waveform

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015