IEEE Solid-State Circuits Magazine - Fall 2015 - 37

input clock that is operating well
beyond the bandwidth of the distribution, the output waveform will be
approximately sinusoidal. However,
if the input waveform experiences a
jitter impulse, as represented by the
dotted line, the difference between
the ideal input versus the jitter
impulse input is effectively a voltage impulse.
If superposition principles are applied, the resulting output waveform
will be a sinusoid added to the impulse response of a low-pass filter.
From the waveforms of Figure 6, it
is possible to observe that multiple
zero-crossing edges will be shifted
from the ideal placement until the
impulse settles. Additionally, as the
bandwidth of the clock network decreases, the tail of the jitter impulse
will increase while the amplitude
of the clock output waveform decreases, thus exacerbating the jitter
amplification effect. As shown in the
figure, this behavior can also be represented in the phase domain as a
jitter impulse response, and LTI principles such as superposition may
apply for sufficiently small jitter
impulse amplitudes. Figure 7 demonstrates the qualitative relationship between the voltage domain
frequency response of a low-pass
filter and the corresponding phasedomain jitter impulse response,
as well as the phase-domain jitter
transfer frequency response, which
passes low-frequency jitter without
modification but amplifies high-frequency jitter.
Conversely, a low-pass jitter transfer response, as shown in Figure 7(b),
can be beneficial to the clock network performance by attenuating
the destructive high-frequency jitter.
Reducing high-frequency jitter components is especially important in
wireline transmitters because the
response causes transmitter symbolwidth variation and pulse distortion
that severely degrades the performance of equalizers. This low-pass
jitter response can be created based
on a voltage domain bandpass filter
response with the resonant frequency

Frequency
Response

Jitter Impulse
Response

Jitter Transfer
Response

(a)

(b)

Figure 7: Examples of relationships between frequency response and jitter transfer for (a) lowpass and (b) bandpass.

tuned to match the fundamental
clock frequency.

Clock Distribution Network Designs
Many examples of tuned clock networks have been demonstrated, and
they have been proven to be beneficial in terms of limiting harmful jitter components and enhancing the
clock amplitudes with lower power.
Another potential method to produce

(ILOs) have emerged as a method that
enable a low-pass jitter transfer response along with low power and complexity. Additionally, ILOs can easily
tradeoff injection-locked transfer jitter
versus ILO-generated jitter by varying
the injection strength.
Another key consideration in the
design of wireline clock distribution
is the impact of device variation, especially as process technologies scale.

The generation of a clock for a local domain
is a task especially critical for high-speed
signaling systems.
an attractive low-pass jitter transfer
response is to incorporate a PLL in the
distribution path, as indicated in the
clock synthesis section. Due to the
area and power overhead as well as
the jitter accumulation that normally
accompanies PLL designs, this may not
be a viable alternative for jitter amplification mitigation in clock distribution paths. Injection-locked oscillators

Device variation can cause delay variation and asymmetries in the clock
waveforms, as well as deterministic
jitter such as duty-cycle distortion,
quadrature clock error, and other
nonidealities. Duty-cycle distortion is
exhibited through asymmetric clock
cycle waveforms (specifically, a mismatch in high-pulse versus low-pulse
widths) and can be a particularly

IEEE SOLID-STATE CIRCUITS MAGAZINE

fa l l 2 0 15

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015