IEEE Solid-State Circuits Magazine - Fall 2015 - 38

destructive form of high-frequency
deterministic jitter that needs to be
monitored and detected to prevent
suboptimal performance.
Although process scaling can be
a negative in terms of variation, it is
possible to take advantage of the increased level of device capacity by
leveraging more comprehensive and
accurate compensation circuitry,

clock domain that can be designed
and validated in a manner similar to
standard digital timing circuits. The
challenge of this type of architecture
is that the I/O cycle time is limited by
the sum of the transmitter (TX) clockto-Q time, the channel latency, the
receiver (RX) setup time, and the TXto-RX clock skew and jitter.
These timing constraints limit I/O

Another key consideration in the design of
wireline clock distribution is the impact of device
variation, especially as process technologies scale.
primarily based on digital circuits.
For example, methods of calibrating primarily through digital means
can be achieved in a very small silicon
footprint and power envelope that potentially enable per buffer correction,
which could be important as process
technology becomes more advanced.

Clock Recovery
One of the most common and simplest forms of link interface clocking
consists of a common clock distributed throughout the entire system.
This approach establishes a unified

data rates to a few hundred Mb/s.
More refined clocking techniques to
scale I/O rates beyond a few Gb/s have
been referred to by some as "serial
I/O" clocking schemes. However, this
term is a misnomer in that these more
advanced techniques are not only
applied to narrow, serial interfaces
but may also be leveraged for wide,
parallel interfaces with equivalent
per-pin rates at much higher aggregate bandwidths.
The two primary classes of
multi-Gb/s clock architectures that
embody these advanced clocking

Clock
Synthesizer

Clock
Distribution

Fwd CK

Data

Figure 8: A general forwarded clock architecture.

fa l l 2 0 15

IEEE SOLID-STATE CIRCUITS MAGAZINE

Clock
Recovery

techniques are forwarded-clock (FC)
and embedded-clock (EC).

Forwarded Clock Architecture
A diagram of a general FC architecture is shown in Figure 8. FC, sometimes referred to more specifically
as source-synchronous clocking,
uses a dedicated clock link sent
from the TX to the RX. This architecture is most often used in wide,
high-aggregate bandwidth links
where the cost and power overhead
of the FC circuits are amortized
across multiple links in the system.
In many cases, FC architectures
utilize matching between the clock
and data circuits to minimize the
impact of transmit induced jitter.
In the ideal scenario, the FC TX and
data TX share a common design and
are synchronized by an identical
synthesizer and clock distribution
tree. This will not only save TX power
and area, it also provides TX jitter
tracking between data and the corresponding RX sampling clock. Practically, matched clock and data latency
is usually not perfectly achieved,
which results in a degradation of the
clock recovery bandwidth, the highest jitter frequency the clock recovery can effectively track. However,
it is usually feasible to constrain
latency mismatch to enable recovery
bandwidths of hundreds of MHz [3].
The FC recovery unit attempts
to center the receiver sample at the
optimum point as measured by the
operating margin (i.e., the time or
voltage margin) or bit-error ratio.
Most FC recovery implementations
allow for arbitrary length mismatch
between the FC and data lines by
detecting the optimum sampling
phase and appropriately shifting
the FC by the optimum amount. If
the TX clock and data circuits are
adequately matched and tolerant to
voltage or temperature fluctuations,
it may be sufficient to optimize the
RX phase only during initialization
or at some periodic interval.
During the training period, it is necessary for the data TX to send a pattern
with a high enough edge probability to

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015