IEEE Solid-State Circuits Magazine - Fall 2015 - 40
Data link performance will continue to scale
with process, circuit, and system innovations,
but it is greatly dependent on high-quality clock
architecture and circuit solutions
Clock
Synthesizer
Clock
Recovery
Clock
Distribution
Clock
Encoder
Data
TX
RX
Figure 10: An embedded clock architecture.
to be instantiated in a design without
significant overhead because there
is little or no globally shared link circuitry. However, there are also many
instances in which EC architectures are
optimized for parallel operation that
allows cross-link sharing of clock synthesizers and distribution and recovery
circuits, which saves power and area at
the cost of design modularity. All ECbased links require timing information
to be encoded in the data to ensure a
high probability of data edge transitions. Examples of data edge encoding
include Manchester encoding, 8B/10B,
64B/66B, or even statistical coding
methods such as pseudo-random bit
sequence scrambling.
As with FC architectures, there are
numerous varieties of EC recovery
links. Two implementations that are
frequently utilized include PI-based
embedded recovery and an oscillator-based embedded recovery.
PI-Based Recovery
Reference
Clock Gen.
PLL
Clock
Distribution
Reference
Clock Gen.
DLL
PLL
PI
Clock
Distribution
TX
Data
RX
Figure 11: A PI-based EC architecture.
40
fa l l 2 0 15
IEEE SOLID-STATE CIRCUITS MAGAZINE
CDR
The RX clock recovery method for
the PI-based architecture aligns the
incoming data phase with a globally or locally synthesized clock
using a frequency mixer circuit. In
most cases, this frequency mixer is
implemented as a multiphase clock
generator followed by a PI and corresponding control logic.
PI-based clock recovery can be
advantageous in area-sensitive applications because much of the RX
circuitry (in addition to the TX circuitry), as shown in Figure 11, may
be shared globally across multiple
links. For example, the PLL, DLL, and
distribution to produce the multiphase clocks for the PI may be shared
between adjacent links. Additionally,
the CDR loop filter that controls the
PI can be implemented using digital techniques. The combination of
these features enables area-efficient
implementation. For this reason, this
architecture is frequently leveraged
for highly parallel EC applications.
Another advantage of a globally
shared PLL at the RX (as well as the TX)
is that a higher proportion of power,
area, and design resources may be
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015
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