IEEE Solid-State Circuits Magazine - Fall 2015 - 41

and accurately analyzing nonidealities
in wireline clocking systems is essential in optimizing performance and
reliability. To optimize and balance
data link performance, power, and
cost, it is crucial that circuit and system designers develop a deep understanding of clocking tradeoffs at all
levels of the link hierarchy-from the
circuit-level implementation to the
system-level architecture.

Reference
Clock Gen.

PLL
XCO

Clock
Distribution

Acknowldgments

Data

I thank Frank O'Mahony, James
Jaussi, and Mozhgan Mansuri for
past collaboration that assisted in
the development of this article.

CDR

References
Figure 12: A CO-based EC architecture.

allocated for the central clock source
because the overhead is amortized
across multiple links. Moreover, any
improvement in the clock quality of
a globally shared resource usually
enjoys a larger return on investment
when compared with resources allocated to multiple instantiations of
local circuitry.

Oscillator-Based Recovery
An oscillator-based embedded clock
recovery architecture uses a dedicated
RX-side controlled oscillator (CO) as

what causes this architecture to deviate from a conventional PLL design.
A primary motivation for CO-based
clocking use is the performance advantages of locking the RX clock synthesizer directly to the TX clock domain.
Because of this, there is no requirement for intermediate frequency mixing or interpolation, which may cause
jitter and a corresponding performance degradation. Furthermore, any
update to the phase of the RX sampling
clock is filtered through the CO loop
filter, which results in a minimum

[1] B. Casper and F. O'Mahony, "Clocking
analysis, implementation and measurement techniques for high-speed data
links-A tutorial," IEEE Trans. Circuits
Syst. I, vol. 56, no. 1, pp. 17-39, 2009.
[2] A. Hajimiri, S. Limotyrakis, and T. Lee,
"Jitter and phase noise in ring oscillators,"
IEEE J. Solid-State Circuits, vol. 34, no. 6,
pp. 790-804, June 1999.
[3] B. Casper, J. Jaussi, F. O'Mahony, M. Mansuri, K. Canagasaby, J. Kennedy, E. Yeung,
and R. Mooney, "A 20Gb/s forwarded clock
transceiver in 90nm CMOS," in Proc. ISSCC
Digest of Tech. Papers, pp. 263-272, 2006..
[4] G. Balamurugan and N. Shanbag, "Modeling
and mitigation of jitter in multi-Gbps sourcesynchronous I/O links," in Proc. 21st Int.
Conf. Computer Design, pp. 254-260 , 2003 .
[5] J. Jaussi, B. Casper, M. Mansuri, F. O'Mahony,
K. Canagasaby, J. Kennedy, and R. Mooney,
"A 20Gb/s embedded clock transceiver in
90nm CMOS," in Proc. ISSCC, 2006 .
[6] J. Alexander, "Clock recovery from random binary signals," Electron. Lett., vol.
11, no. 22, pp. 541-542, 1975.

About the Author

Wireline frequencies are normally much greater
than the on-chip data-path frequencies.

the central clock recovery component,
as shown in Figure 12. This is sometimes referred to as PLL-based clocking because it uses a CO as the clock
source, with the RX functioning as a
phase detector and the CDR circuit acting as a loop filter. The combination of
these components forms a loop that
locks to the mean phase of the incoming data. The fact that the loop must
lock to a reference source that may
not have consistent edge transitions is

amount of clock glitches and jitter. As
mentioned previously, another advantage af a CO-based architecture is that
the RX clocking is instantiated locally,
which permits design modularity.

Summary
Data link performance will continue to
scale with process, circuit, and system
innovations, but it is greatly dependent on high-quality clock architecture
and circuit solutions. Understanding

Bryan Casper is the director of the
PHY Research Lab and senior principal engineer with Intel Labs, based in
Hillsboro, Oregon. He currently leads
the organization responsible for all
high-speed PHY research at Intel Corporation in the electrical, optical, and
short-distance mmWave domains. In
1998, he joined the Performance Microprocessor Division at Intel and contributed to the development of the Intel Pentium and Xeon processors. Since
2000, he has been a circuit researcher,
contributing to the development of I/O
self-test technology, signaling analysis
methods, high-speed I/O circuit architectures, and multiple I/O standards.

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