IEEE Solid-State Circuits Magazine - Fall 2015 - 44

data rate that can be communicated, and the TX and RX power consumption. For example, we wish to
transport data at a rate of 40 Gb/s
through a channel that has 25 dB

of loss at 20 GHz while the transceiver (TRX) must consume less
than 1 mW/Gb/s (40 mW).
This brief perspective reveals that
today's high-performance, high-speed

TX Driver
VDD
RT

RX

RT

R0
2RRX

M1

R0

M2
ISS

100

Bipolar/BiCMOS
CMOS

10

Pdr =

Year
Figure 3: The speed of MUX and DMUX circuits versus time.

Bipolar/BiCMOS
CMOS

10

1.0

GaAs

2014

Vswing
VDD,
R0 RT

(1)

where Vswing denotes the peak differential voltage swing delivered to
the channel. If the driver is modified to generate rail-to-rail swings,
(1) can be reduced to V 2swing / (R 0 R T ) .

100

Bipolar/BiCMOS
CMOS

10

1.0

0.1

1986
1988
1990
1992
1994
1996
1998
2000
2002
2004
2006
2008
2010
2012
2014

0.1

1996
1998
2000
2002
2004
2006
2008
2010
2012
2014

CDR Data Rate (Gb/s)

100

2012

2010

2008

2006

2004

2002

2000

1998

1996

1992

1994

1990

1988

1986

1984

1.0

Equalizer Data Rate (Gb/s)

MUX, DMUX Data Rate (Gb/s)

Figure 2: The problem of output driver power dissipation.

systems have grown from extensive work on a multitude of building
blocks: MUXs and DMUXs, PLLs and
frequency dividers, equalizers, and
CDR circuits. We therefore study the
history with the aid of the evolution of
some of these building blocks.
It is important to note that the
voltage swing delivered by the TX
driver in Figure 1 to the copper
channel has not scaled much with
technology due to signal-to-noise
ratio limitations at the receive end.
For a given channel characteristic
impedance, e.g., 50 X, this means
that the driver draws a weakly scalable power. This issue becomes
more severe at rates higher than a
few gigabits per second as the driver
must incorporate back-termination,
on-chip resistors to suppress secondary reflections. Figure 2 depicts
an example where the R T resistors
reduce reflections returning from
the receive end due to the mismatch
between R RX and R 0 . In this case,
the driver consumes a power of

Year

Year
Figure 4: The speed of CDR circuits versus time.

44

fa l l 2 0 15

IEEE SOLID-STATE CIRCUITS MAGAZINE

Figure 5: The speed of equalizers versus
time.



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015

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