IEEE Solid-State Circuits Magazine - Fall 2015 - 46

Serial Link Power Efficiency (mW/Gb/s)

10,000

Of greatest interest to us is the PE of
the overall serial ink. As shown in Figure 9, the normalized power of CMOS
designs has dropped from 1.2 W/Gb/s
to about 6 mW/Gb/s, with a few
exceptions around 1-2 mW/Gb/s.
This factor of 200 over 20 years is
less impressive than those observed
for CDR and equalizer circuits and
can be attributed to three issues: the
weakly scalable power consumed by
the TX output drivers, various functions that have been added to TRXs,
and, most notably, the push for higher
speeds and hence the need to operate
with nonlinear power-speed tradeoffs.
Nevertheless, if sustained, this 30%
per year reduction would lead to a link
PE of about 0.4 mW/Gb/s by 2025.

Bipolar/BiCMOS
CMOS

1,000

100

10

1.0

2014

2012

2010

2008

2006

2004

2002

2000

1998

1996

1994

1992

1990

1988

0.1

Year
Figure 9: Serial link PE versus time.

signal processors later, decision-feedback equalizers (DFEs) did not appear
in the analog domain until the 2000s.
This is because feedback timing constraints limited the speed of DFEs but
not the CTLEs.
The term "serial link" was used, perhaps for the first time, in 1991 to refer to
a 1.5-Gb/s TRX [3]. Figure 6 plots TX, RX,
or TRX data rates as a function of time.
Except for a few bipolar designs, the
space has been governed by CMOS technology as integration proves essential
here. It is remarkable that the speed in
CMOS has climbed by a factor of 60 in 20
years. If this trend continues, the serial
data rate will exceed 400 Gb/s by 2025!
The problem of channel loss at
high speeds has motivated work on
nonbinary signaling schemes that
consume less bandwidth for a given
data rate. For example, PAM-4, previously investigated in the late 1990s
[4], has reemerged as a plausible candidate [5], [6]. Affording a twofold
bandwidth reduction, PAM-4 nonetheless requires more complex circuit
design and a higher amplitude resolution in the receiver.

46

fa l l 2 0 15

Power Efficiency
With a large number of I/Os, the power
consumed by each link between chips
becomes critical. In this section, we
examine the historical trends in the
power efficiency (PE) of wireline TRXs
and some of their building blocks.
Figure 7 plots the PE of CDR circuits
as a function of time. Since the CDR
speeds in the late 1980s were quite
low (Figure 4), their normalized performance to 1 Gb/s translates to several
watts of power. Bipolar implementations continued to improve their PE until early 2000s, after which CMOS took
over. We observe that the CDR normalized power dissipation has fallen by a
factor of 25,000 over 25 years, i.e., by
about 50% per year. If this trend continues, CDR circuits will consume about
4 n W/Gb/s in 2025.
The PE of equalizers is depicted
in Figure 8. As with CDR circuits,
equalizers have seen a dramatic reduction in their normalized power,
by about a factor of 3,000 over 15
years. This 70% per year improvement would yield an equalizer PE of
1 n W/Gb/s in 2025.

IEEE SOLID-STATE CIRCUITS MAGAZINE

References

[1] T. H. Hu and P. R. Gray, "A monolithic
480 Mb/s parallel AGC/decision/clockrecovery circuit in 1.2-um CMOS" IEEE
J. Solid-State Circuits, vol;. 28, pp. 1314-
1320, Dec. 1993.
[2] M. E. Austin, "Decision-feedback equalization for digital communication over dispersive channels," Tech. Rep. 347, Lincoln
Lab., Aug. 1967.
[3] R. C. Walker, T. Hornak, C. S. Yun, and
J. Doernberg, "A 1.5 Gb/s link interface
chipset for computer data transmission,"
IEEE J. Selected Areas Commun., vol. 9, pp.
698-703, June 1991.
[4] R. Farjad-Rad and M. Horowitz, "An equalization scheme for 10Gb/s 4-PAM signaling over long cables," in Proc. Mixed Signal
Conf. 1997.
[5] A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh,
T. He, A. Momtaz, and J. Cao, "A 36 Gb/s
PAM4 transmitter using an 8b 18 GS/s
DAC in 28 nm CMOS," in ISSCC Dig. Tech.
Papers, Feb. 2015, pp. 58-59.
[6] J. Kim, A. Balankutty, A. Elshazly, Y.
Huang, H. Song, K. Yu, and F. O. Mahony,
"A 16-to-40 Gb/s quarter-rate NRZ/PAM4
dual-mode transmitter in 14nm CMOS,"
in ISSCC Dig. Tech. Papers, Feb. 2015,
pp. 60-61.

About the Author
Behzad Razavi (razavi@ee.ucla.edu)
is a professor of electrical engineering
at the University of California, Los Angeles, where he conducts research on
analog and high-speed circuits. He has
received seven awards at ISSCC, CICC,
ESCCIRC, and VLSI Circuits Symposium
for his research and four awards for
his teaching. His books have been published in seven languages. He received
the 2012 Donald Pederson Award in
Solid-State Circuits.



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