IEEE Solid-State Circuits Magazine - Fall 2015 - 53
Looking Future
to
the
Projected requirements for wireline
communications technology
Hirotaka Tamura
I
believe that engineers and academics,
whatever their field, should occasionally
spend some time trying to forecast the
future. They can then try and prepare for
it by deciding what activities to prioritize
now. This article represents an attempt to explore the
future of wireline communications. To avoid making it
too long, its focus will be limited to wireline technology
for chip-to-chip communications in computer systems.
The forecast I offer here is based on an extrapolation
of technical trends. Of course, this has its limits. First, the
further into the future an extrapolation is, the greater its
potential for error, e.g., due to the emergence of a previously unknown technology. Furthermore, the very basis
of extrapolation, i.e., the assumption that the future is
totally determined by the past, is seldom true.
We are now reaching the point where the transistor scaling that has supported Moore's law for the
past 50 years will come to an end-probably
within the next five to ten years. To face this
challenge, various new technological measures will be taken, making forecasts based on
simple extrapolation difficult. Nevertheless, at
the risk of being proved wrong, I will try to
forecast the future of wireline communications beyond the end of scaling.
To prevent a future forecast
from being excessively constrained by past trends,
it should reflect a certain personal vision of
the future. However,
there is a danger that
Digital Object Identifier 10.1109/MSSC.2015.2477017
Date of publication: 2 December 2015
1943-0582/15©2015IEEE
IEEE SOLID-STATE CIRCUITS MAGAZINE
fa l l 2 0 15
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