IEEE Solid-State Circuits Magazine - Fall 2015 - 58

Achieving a hundredfold performance
improvement in ten years' time will require
a review of compute-operation methods.
with every layer of cache hierarchy,
the bandwidth from that layer to the
outside will decrease exponentially
(bandwidth tapering) [6-7]. As cache
capacity increases, the decrease in
bandwidth will become greater. For
simplicity, let us assume that cache
capacity will increase by 1/x 2 (where
x is the dimensional scaling factor)
as long as scaling continues. Let us
further assume that the cache-hit
rate is proportional to the square

ISSCC 1996-2015

1,000
Power Efficiency (mW/Gb/s)

root of cache capacity [9], and so the
decrease in the processor's B/F ratio
will be proportional to x.
To determine the performance
trend of wireline transceivers, data
presented at the International SolidState Circuits Conference from 1996
to 2015 (Figures 7 and 8) will be
extrapolated and used. Between 2005
and 2015, the data rate per transceiver pin has doubled every two
generations, resulting in a trend

100

×0.7/Two Years

0.1
1996 1998 2000 2002 2004 2006 2008 2010 2012 2014 2016 2018 2020
Year
Figure 8: Transceiver energy efficiency.

1,000

Etot/Echip

N=5
N=6
N=7
100

1
2
Energy Tapering Factory γ

Figure 9: The effect of bandwidth tapering.

fa l l 2 0 15

IEEE SOLID-STATE CIRCUITS MAGAZINE

proportional to 1/x (Figure 7). Although there is a great deal of variance in the data for transceiver
switching energy (Figure 8), let us
assume that it decreases by a factor
of 0.5 every two generations, i.e., the
decrease is proportional to x.

Methods to Exceed
Performance Limit
Under the limiting factors mentioned
earlier, methods other than scaling
will be required to sustain the increasing performance trend indicated in
Figure 1 for another ten years or so.
This is because scaling down to the
10-nm node will only improve power
efficiency by a factor of ten or less
(Figures 4 and 6).
The majority of researchers
agree that one way to improve performance is by hardware specialization. Generally, the power efficiency
of a circuit dedicated to a specific
application is high, sometimes up to
a thousand times higher than that of
general-purpose processors [8]. For
some applications, the power efficiencies of field-programmable gate
array (FPGA) accelerators are tens of
times higher than that of processors
[10], [11].
The problem with hardware specialization is the loss of versatility, making software development
difficult. For example, an FPGA is
programmable at the gate level, and
highly specialized circuits can be
realized, but, compared with a GPU,
writing the necessary software is
quite difficult. Furthermore, note
that Horowitz [8] compared only the
power efficiency of processors but
did not include the energy required
for the transfer of external data or
for memory access. Including the
external data-move energy will further reduce the predicted system
power efficiency.
Even when using specialized
hardware, it is still important to
reduce the energy consumption
required for the transfer of external
data. Currently, this energy is much
larger than for compute operations, and so the pressure to reduce

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015