IEEE Solid-State Circuits Magazine - Fall 2015 - 59
Output yj
f
f : Sigmoid Function
Neuron
Weight wij
Output
x1
Operation
Data Flow
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-6
Output
xn
Input xi
Local
Data
Input
-4
-2
0
2
4
6
Weighted Sum of Inputs
(a)
(b)
Figure 10: (a) an artificial neuron and (b) a neural network.
energy will be greater for wireline
transceivers than for compute circuits. Therefore, packaging technology and data-centric architectures
need to be adopted to minimize the
data-transfer distance and the need
for data transfer, respectively.
Signals closest to the compute
chip have the highest data-transfer
bandwidth due to bandwidth tapering. Therefore, reducing the energy
required for data transfer to the immediate neighborhood of a chip will have
the highest priority. The required
bandwidth should be reduced exponentially with the distance from the
chip by using mechanisms like cache
hierarchy, network topology, or some
form of data filter. However, as the
distance to the chip becomes greater,
the required switching energy of the
data-transfer link becomes larger.
Let us assume that we have a hierarchy of signaling (e.g., chip, package, board, and cabinet) and that the
energy for signal transmission per bit
will increase by a factor c for each
extra hierarchical layer around the
chip. When the chip's total I/O energy
per operation is expressed as E chip, the
total energy of the signal transmission
To achieve a performance improvement ratio in excess of a few
hundred, the energy associated with
To reduce data-transfer energy by several orders
of magnitude, the physical arrangement of
the connections between various specialized
operation circuits will be of critical importance.
system in the nth layer E tot is given
by the following equation:
E tot = E chip
1 - cn
.
1-c
(1)
To minimize the total data-transfer
energy of the system, it is desirable to
set the value of c to one or less: for
example, c < 0.5. The reason is that if
c < 0.5, the value of (1) will be equal
to or less than double the data-transfer energy of the neighboring layer
nearest to the chip, even if the number of layers for signal transmission,
n, is very large; however, if c > 1, it
increases rapidly with n (Figure 9).
data transfer (including memory access) should be reduced to the very
minimum, and, at the same time,
highly efficient circuitry is required.
To reduce memory access to the barest minimum, we should probably
shift to some kind of non-Neumann-
type architecture. In addition, information processing different from
ordinary logic operation may be
required. An example of such operation can be found in a neural network
[12]. There is also the extreme example of quantum annealing [13], where
solutions for NP-hard (i.e., nondeterministic polynomial-time-hard)
IEEE SOLID-STATE CIRCUITS MAGAZINE
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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015
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