IEEE Solid-State Circuits Magazine - Fall 2015 - 62

Summary
A tenfold increase in computer performance over five years was hypothesized, and the obstacles that
must be cleared by wireline communications technology to achieve this
were examined. In current computer
systems, as a result of the fact that
processors and memory have historically evolved separately, the energy consumed by data transfer and
memory access is about two orders
of magnitude greater than that consumed by compute operations. For
the coming five-year period, where
the target for performance improvement is tenfold that of the present,
performance is to be improved by
placing more emphasis on reducing the energy for data transfer and
memory access than for operations.
This being the case, signal transfer
at the layer closest to the processor
must be reduced to sub-pJ/bit levels.
Achieving a hundredfold performance improvement in ten years'
time will require a review of compute-operation methods. For example, the frequency of data access
required to perform the information-processing task will need to be
reduced to several percent of its current level. Compute operations that
employ structure, as in FPGAs, must
be adopted as the main method. Concurrently, the energy needed for data
transmission between chips must be
lowered to sub-0.5 pJ/bit levels.
Performance improvements beyond this will need to retain the
Neumann-type architecture and
fully use an algorithm based on a
connection structure (such as a
neural network). Even for normal
logic operation, a completely integrated structure for memory and
operation on the chip will become
necessary. The major target for
wireline communications technology in this time frame must be to
flexibly achieve these diverse chipinterworking structures.
Another item not discussed fully
in this article is form, i.e., the physical arrangement of system components. To reduce data-transfer energy

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by several orders of magnitude, the
physical arrangement of the connections between various specialized
operation circuits will be of critical
importance. To drastically reduce the
energy for data transfer, a somewhat
extreme approach may be necessary.
An obvious example of this kind
of form can be found in the human
brain. There, areas of gray matter,
which are a collection of neurons for
conducting operations, are connected
by white matter, which is a collection of wiring (axons) for transmitting
signals. The white matter, at 700 ml,
has half the volume of the gray matter, with an energy consumption of
approximately one-third or about 5 W
[15], but the entire wire length is extremely long at 1.6-1.8 x 108 m.
Just as we do not need to completely imitate a bird to build a plane,
future computers will not need to
imitate the brain exactly, but the
existence of this kind of interworking method is very suggestive. Will
there be electronic white matter in
our future computing systems?

Acknowledgments
I would like to thank Ryuhei
Sasagawa for creating performance
trends of CMOS logic from CAD
data, Prof. Ali Sheikholeslami of the
University of Toronto for valuable
discussions and feedback, and Prof.
Kofi Makinwa of Delft University of
Technology for editorial support.

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IEEE SOLID-STATE CIRCUITS MAGAZINE

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About the Author
Hirotaka Tamura received his B.S.,
M.S., and Ph.D. degrees in electronic
engineering from Tokyo University,
Japan, in 1977, 1979, and 1982, respectively. He joined Fujitsu Laboratories
in 1982. After being involved in the
development of different exploratory
devices, such as Josephson junction
devices and high-temperature superconductor devices, he moved into the
field of CMOS high-speed signaling in
1996 and got involved in the development of a multichannel high-speed
I/O for server interconnects. Since
then he has been working in the area
of architecture- and transistor-level
design for CMOS high-speed signaling
circuits. He is a Fellow of the IEEE.
http://www.cisco
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