IEEE Solid-State Circuits Magazine - Fall 2015 - 67

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Increase Integration Difficulty

At Last Metal

At First 10x Level
At First 4x Level
At 1x Level

Lower Chip Wireability

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also called redistribution layers
(RDLs). The RDLs can be very
useful when the bumps to the
package do not align with TSVs.
Typically up to two RDLs may be
used (especially for power distribution), and these provide a good
deal of design flexibility. The
RDLs also allow for the fabrication of passive components such
as inductors in a way that does
not inhibit wiring.
n bump, copper pillar, and assembly development. Assembling
strata is typically at a finer bump
pitch of ~50 nm or below for
interstrata interconnects. This
fine pitch needs much greater
tolerance and die flatness to be
attached, as well as a few nm tolerance in the bump/pillar height.
At these pitches, the standard
mass reflow used in conventional
bump joining is not possible
because the solder is compressed
and squeezes out, causing interbump shorts. Instead, we need to
use thermal compression bonding (TCB). In TCB, pressure is
applied at a high temperature to
bond the pillar of one stratum
to the pad of the other. Assuring
contact across a full die for every
pillar is a difficult, and this continues to be a challenging area.
The throughput of thermal compression bonders continues to
be low, and yield of this step
is not where it should be, especially for large die with many
connections. Bond reliability is
also challenging.
Warpage. Finally, warpage needs to
be controlled to minimize stresses. In addition, the TSV itself has
a moderate stress field associated
with it. This stress is significantly
lower than the stress applied along
the channel to improve device mobility. Even so, long channel-linear
threshold voltage is modulated by
TSV stress and is today managed
by keep-out zones (KOZs) [8]. Typically, a KOZ may be 2-5 nm from
the edge of the TSV. In future, it is
expected that modified models for

Not All Levels Shown

Figure 5: TSVs may be introduced in a hierarchical wiring system. At low levels, less wiring blockage occurs, but there are more integration challenges. Today's relatively large TSVs are optionally
integrated at wiring levels, where dimensional discrepancies between the wiring level and the
TSV are minimal. One to two wiring levels above the TSV can relive a significant amount of wiring
congestion.

devices within the KOZ will be extracted so that designers will have
greater freedom to place devices
as closely as possible to the TSV.

TSV Integration
Another important issue to address
is how to integrate (or capture) TSVs
in the processing flow. We illustrate
this schematically in Figure 5.
DRAMs typically have three or
four metal layers, and we usually
integrate the TSV at the second
metal level, with an additional level
or two above the TSV. In logic, things
get more complex. TSVs block both
devices and wiring completely. So
this is a major disruption for place
and route.
Integrating the TSV at the lower
levels of the wiring hierarchy would
minimize this problem. However,
from a processing perspective,
this is more difficult as there is a
large size disparity between the
TSV and the wiring and via pitches
at the lower levels of the hierarchy
(+ nm vs + 100 nm) . This problem
is much more tractable at the upper
levels of the hierarchy where dimensions are comparable. These levels
are also thicker and better able to

withstand the stresses caused by the
thermal coefficient of expansion difference between silicon and copper
(the so-called pistoning effect).
It is possible to have a wiring
layer or two above the TSV capture
level that can allow for wiring over a
TSV. We also have porosity rules that
allow for wiring at even lower levels
to penetrate through TSV farms. We
also point out that at 50- nm pitch for
both bumps and TSVs, we are mainly
connecting power and I/Os. Even in
a 2-D case, these escape at the fat
wire level, so we are not compromising much in this fat wire capture
scheme for the TSV.
Furthermore, integrating the TSVs
at the upper levels of the hierarchy
allow us to bypass the lower levels
of the hierarchy, which tend to have
higher resistance. This is important
when trying to minimize IR losses.

Synchronizing Clock Networks
One final design comment relates
to the sharing and synchronization
of high-speed clocks across strata.
This is perhaps very important in
high-performance logic. The clock
network is also usually distributed across the die using the fat

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015