IEEE Solid-State Circuits Magazine - Fall 2015 - 68

(a)

(b)

Figure 6: (a) A ceramic MCM. Multiple die are assembled on a multilayer ceramic substrate.
Because vias are mechanically punched, dimensions are rather larger, and this method of integration does not scale well. Going to organic laminates is only slightly better. (Courtesy of IBM.)
(b) A heterogeneous integration of SiGe BiCMOS die with a 45-nm SOI eDRAM application-specific
integrated circuit on a silicon interposer mounted on a ceramic substrate. On the interposer, bandwidths are in excess of two total bandwidth servers/s. (Courtesy of Sematech and IBM.)

or superfat wiring levels. In an F-F
embodiment, these levels are proximate to both the TSVs and inter-die
bumps, and it turns out that merely
meshing the clock network across
the two strata produces satisfactory
clock synchronization [9].

Two Applications
We now look at two main applications and detail the design considerations for each: one is heterogeneous
integration using an interposer; the
other is memory stacking, which
has seen the widespread use of
3-D stacking with some significant
impact on footprint, active signals,
and power reduction. In fact, 3-D
has made possible some spectacular architectural changes in memory
organization and use.

Interposers
Historically, the concept of an
interposer derives from the classical multichip module (MCM) shown
in Figure 6(a). As can be seen, the
ceramic MCM was rather bulky and
gave way to the organic MCM used
almost exclusively today. The drawback with either of these MCMs is
the relatively coarse pitch of both
the vias and the wiring (~several
hundred nm ).
The silicon interposer provides
a silicon-based layer on which multiple die can be integrated at much
tighter pitch. This allows much
tighter interconnection of chips, as

fa l l 2 0 15

well as the ability to integrate a wide
variety of chips fairly intimately.
We show such a case in Figure 6(b),
where we have integrated two 90-nm
silicon germanium (SiGe) bipolarjunction transistor and CMOS
transistor technology (BiCMOS)
transceivers with a 45-nm siliconon-insulator (SOI) CMOS digital
processor. The interposer was fabricated in simplified 90-nm process
with four wiring levels and deeptrench-based decoupling capacitors.
Interposers typically have only
passive components: wiring, capacitors, and inductors. The interposer
does not eliminate the need for a
package, and, in this case, a ceramic
package closely matched to silicon
in thermal coefficient of expansion
was employed because of its superior dielectric and mechanical properties. Inputs and outputs to the
module were routed through this
package to the interposer.
The key challenges in interposer
design are as follows.
■ Ensuring adequate analog bandwidth and the correct impedance
on the input/output ports, and
avoiding crosstalk-especially for
chip-chip communication. This
was done using buried and fully
shielded stripline traces on the
interposer. Shielding is mandatory as the silicon is conductive.
■ Providing power supply distribution and decoupling. Decoupling
was accomplished by embedding

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deep trench capacitors [10]
around each TSV to handle high
current spikes from the digital
logic. The ability to integrate passives is often referred to as valueadd interposers.
Interposers are often the first
step in 3-D integration because they
do use some of the key technologies
used in 3-D, such as TSVs, wafer
thinning, and fine-pitch interconnects and assembly, as well as RDLs.
However, they do not have any
active devices; and, since they are
typically used to integrate multiple
die laterally, they are larger-sometimes extending beyond the reticle
field. This makes printing features,
warpage control, and assembly
more challenging, but because the
interposer itself has less wiring
and no devices (except perhaps passives). they are usually less warped.

3-D DRAMs Design Considerations
A key advantage of 3-D is the capability of increasing the density naturally
by stacking multiple chips vertically. The 3-D chip stacking approach
allows a significantly shorter signal
path than the conventional 2-D chipintegration approach. The short signal
path also reduces the dynamic power
dissipation due to lower wiring capacitance and fewer redriver circuits. The
high-density, short signal path and
dynamic power reduction made possible using 3-D stacking provide significant advantages to high-density
and high-bandwidth DRAMs.
The year 2012 introduced significant evolution in 3-D DRAM with the
hybrid memory cube (HMC) [11]. The
key feature of the HMC is the heterogeneous stacking of DRAM and the logic
chip, where the logic chip on the bottom converts wide I/O DRAM data to a
high-speed serial link (10 G/s, 15 G/s,
and 30 G/s). An alternative approach,
high-bandwidth memory (HBM) [12],
employs a simple wide I/O communication using a fine pitch silicon interposer. Both HMC and HBM realized
>128 GB/s bandwidth, an increase
of >10× over the double data rate
(DDR)-3/4 standard.

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015