IEEE Solid-State Circuits Magazine - Fall 2015 - 73

C4 = 2 µbump (150 µm)
Decoupling, Switch, Pump, Clock

µbump (75 µm)

Super FAT BEOL

Etc.
VDD

GND
VDD C4

VCS C4

VCS TSVMEM

VDD µbump
VDD TSVµP

VDD

IPW

GND
GND TSV
GND µbump
GND C4

14-nm eDRAM 1.125-Mb IP
(211.2 µm × 284.8 µm)

VCS C4

18.7 Mb/mm2

VDD

C4
TSV

TSVXP = 3 × C4 (450 µm)
= 2 × IPw (2 × 211 mm x) + TSVKOZ(25 µm → 28 µm)

µbump (Power)
µbump (Signal)

Figure 11: A case study showing the preferred C4, μbump, and TSV floor plan using 14-nm eDRAM. (Courtesy of IBM.)

design parameters we must adhere
to are as follows: 14-nm eDRAM IPW
is 211 nm, and TSVKOZ > = 25 nm,
C4 pitch > = 150 nm.
As shown in Figure 11, these parameters suggest that using n = 2, and
m = 3 may be a better choice: because
we can put two of the IPs (211 nm ×
2 (n = 2) = 422 nm) in 450 n m, the
remaining space (450 nm − 422 nm
= 28 nm), which is larger than the
TSVKOZ of 25 n m, can be used for TSV
allocation. Using 150 nm C4P, a TSVXP
of 450 nm will align to every third
C4 location.
Although we could save 3 nm by
using TSVKOZ min of 25 nm, it is preferred to keep both TSV and C4 on a
common grid design for uniformity
and simplicity. The nbump uses one
half of the C4 pitch (150 nm ), resulting in 75 nm. The C4, nbump,
and TSV arrangement in the vertical

dimension are more flexible because
there is no eDRAM IPW restriction.
In this example, we assume that C4
pitch, TSV pitch, and n bump pitch
are 150 nm , 75 nm , and 75 nm, respectively, so that C4s overlap both a
TSV and n bump every 150 nm .
The power TSVs between two
adjacent units (in this case, each
having two memory macro blocks
horizontally) are coupled to nbump
(75 nm pitch) over the array using
the corresponding Vdd and ground
super-fat wires. The TSVs designated
to pass power through to the nP are
all coupled directly to the external C4
(150- nm pitch) on the back side of
the memory chip. The remaining TSVs
(TSVMEM), which are offset from the
backside C4 pattern, are assigned to
the power (VCS) for memory as shown.
Because of F-F design data, communication between memory and nP does

not need to use TSVs. The nbumps for
signaling are arranged over the array
and driven by circuits in the peripheral
area between memory macro blocks, resulting in zero penalties.
The space between the power
TSVs are the natural location for
placing decoupling capacitance. For
DRAM design, the space may also
be used for word-line voltage generator circuits and power isolation
switches to preventing dc fails. For
a larger chip, the space may be used
for clock redriver circuits.
This working example points
out the difficult tradeoffs in allocating bumps, n -pillars, and TSVs
to achieve an optimal stack design.
Codesign of the two chips and synergy with the process developers are
critical to optimize the overall stack
design without pushing technology
features beyond reasonable limits.

IEEE SOLID-STATE CIRCUITS MAGAZINE

fa l l 2 0 15

73
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015
