IEEE Solid-State Circuits Magazine - Fall 2015 - 74

Furthermore, a similar situation also
exists for interposer design. As can
be seen, this kind of tradeoff is currently performed manually, but we
will need to formalize the process
and develop automated tools that can
be used by the design community.

Summary
Three-dimensional integration-both
interposers and die stacking-is gaining
increased acceptance. From a technology perspective, several challenges still
remain: thin die handling, fine pitch
interconnect, and die-warpage induced
assembly issues. From a design perspective, we do not necessarily have
robust tools to do a comprehensive
design as we would a conventional
system on chip. However, in the custom design realm, such as in memory
design of both main memory and cache
memory, we have made significant
progress and the use of 3-D die stacking is proliferating at a very reasonable
pace. It also turns out that memory subsystems benefit immensely from the
adoption of 3-D memory.
Designing for 3-D needs to comprehend the nuances of TSV placement as well as reach a good understanding of the thermomechanical
constraints and implications. Uniform power delivery through TSVs
and n bumps is an area that needs
special attention. TSV models including KOZs and even detailed device
characteristics of devices close to
TSVs are well understood. 3-D technology still places some design constraints, mainly relating to interposer
size, metal content, and bump pitch.
Even so the technology is ready for
many prime-time applications.

Acknowledgments
The authors would like to thank
their colleagues at IBM, GlobalFoundries, and the University of
California at Los Angeles for their
valuable insights and contributions.

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IEEE SOLID-STATE CIRCUITS MAGAZINE

About the Authors
Subramanian S. Iyer (s.s.iyer@ucla.
edu) received his B.Tech. degree from
IIT-Bombay and his Ph.D. degree from
the University of California at Los Angeles (UCLA). He has been with the
IBM T.J. Watson Research Center and
later the IBM Systems and Technology Group, where he was appointed
an IBM fellow and served until recently as director of the Systems
Scaling Technology Department that
included advanced packaging development. He is currently the Distinguished Chancellor's Professor of
electrical engineering at UCLA. He has
published over 250 papers and holds
over 70 patents. His current technical
interests lie in the area of advanced
packaging and 3-D integration for
heterogeneous system-level scaling,
as well as in developing a long-term
semiconductor and packaging road
map for logic, memory, and other
devices. He is an IEEE Fellow and a
Distinguished Lecturer of the IEEE
Electron Devices Society as well as a
member of its Board of Governors. In
2012, he received the IEEE Daniel Noble Medal for emerging technologies.
Toshiaki Kirihata received his B.S.
and M.S. degrees in precision engineering from Shinshu University, Nagano, Japan. In 1986, he joined IBM
Research, Tokyo Research Laboratory,
and in 1996 transferred to the IBM T.J.
Watson Research Center and later to
the IBM Semiconductor Research and
Development Center. He is currently
with GlobalFoundries, where he manages the design department for system scaling technology. His research
interests include high-performance
embedded DRAM, embedded nonvolatile memory, 3-D memory, and
hardware security. He is a coauthor
of CMOS Processors and Memories and
Circuits for Emerging Applications,
contributing to chapters on eDRAM
and intrinsic chip ID using eDRAM,
respectively. He is a Senior Member
of the IEEE and an IEEE Custom Integrated Circuits Conference Committee member on memory.
http://www.sony
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015
