IEEE Solid-State Circuits Magazine - Fall 2015 - 90

people

JSSC Best Paper Award 2013

T

The 2013 IEEE Journal of Solid-State
Circuits (JSSC) Best Paper Award was
given to "A 14-b 80-ms/s SAR ADC with
73.6-dB SNDR in 65-nm CMOS" by Haiyang Zhu, Hongxing Li, Steven Decker,
Junhua Shen, and Ron Kapusta. The
paper was published in the December
2013 issue of IEEE Journal of SolidState Circuits (vol. 48, no. 12, pp.
3,059-3,066). The authors received
their award at the IEEE International
Solid-State Circuits Conference (ISSCC)
in San Francisco, California.

Abstract
A 14-b SAR ADC is presented that
achieves 73.6-dB SNDR at 80 ms/s
while using a 1.2-V-only supply. To
overcome throughput limitations that
are common to conventional SAR ADCs,
several techniques are proposed.
First, a flash sub-ADC is utilized to
resolve the five most significant bits.
quickly prior to SAR sequential decisions of the least significant bits.
Digital Object Identifier 10.1109/MSSC.2015.2474260
Date of publication: 2 December 2015

90

FA L L 2 0 15

Coauthors Haiyang Zhu, Hongxing Li, Steven Decker, Junhua Shen, and Ron Kapusta accepting
the Society's 2013 JSSC Best Paper Award from SSCS President Bill Bidermann at ISSCC 2015.

Second, the DAC operation is timeinterleaved by a factor of two, increasing speed while allowing a single comparator to be shared between
all DACs. Third, fully on-chip DAC
charge redistribution allows the DAC
settling time to be improved by more
than an order of magnitude compared
to conventional techniques. Finally,
the ADC is fully self-timed through

IEEE SOLID-STATE CIRCUITS MAGAZINE

the use of a replica timer circuit to
take full advantage of the fast DAC
settling and comparator decisions.
Despite the increased speed, the
ADC consumes only 31.1 mW and occupies a core area of 0.55 mm2.
-Abira Sengupta



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