IEEE Solid-State Circuits Magazine - Fall 2016 - 10

A C ircu it for All Season

Behzad Razavi

TSPC Logic

Since its introduction in the 1980s,
true single-phase clock (TSPC) logic
[1] has found widespread use in
digital design. Originally proposed
as a high-speed topology, the TSPC
structure also consumes less power
and occupies less area than other
methods. In this article, we study
the properties of this logic family.

an indeterminate logical value. This
four-transistor dynamic implementaissue can be resolved by delaying the
tion. This approach, however, required
second stage's clock or by placing an
two nonoverlapping clock phases
inverter at the output of each stage.
so as to avoid transparency during
Shown in Figure 2,
(slow) clock transitions.
the latter method is
That is, clock generacalled"Domino"logic[3].
tion and distribution
Originally
Note that this family
had to deal with not
proposed as
performs operations
only skews but the
a high-speed
using NMOS tra nloss of timing due to
topology, the
sistors, with p-type
nonoverlap intervals,
TSPC structure
switches acting as
making single-phase
also consumes
only reset devices.
clocking more attractive.
less power and
Domino, however, is
Figure 1(b) depicts
occupies less
a noninverting circuit,
a single-phase approach.
area than other
prohibiting some logMerged with the dy methods.
ical functions [4].
namic latches, the logic
The inverters in
is realized by NMOS
Domino logic consume power while
or PMOS devices in alternate stages
realizing no particularly useful func(NMOS and PMOS blocks, respection. We then consider including
tively). Here, when the clock (CK) is
dynamic logic within the inverters.
low, node X is precharged to VDD,
and when CK goes high, the N block
Shown in Figure 3, the result is called
is enabled and, according to the
"NORA" logic [5], and the cost is two
inputs, keeps the ONE or discharges
clock phases.
it to ZERO. The principal issue here
Both Domino and NORA circuits
is that the second stage begins to
suffer from charge sharing; for examevaluate while the first precharges X ,
ple, when CK goes high in Figure 2,
C X loses charge to C P if M1 is on and
a race condition that can lead to a
if VX must remain nominally high.
partially charged level at Y and hence

Background
In the early 1980s, the design of highspeed digital CMOS circuits faced
some interesting challenges. One
general issue was related to clock distribution in complex chips; heavy capacitive loading and long interconnects
caused both slow transitions and skew,
making it especially difficult to distribute multiple, high-speed clock phases.
On the other hand, it had already been
recognized that dynamic logic afforded
simpler, faster circuits that also occupied less area. For example, "clocked
CMOS" (C2MOS) logic, introduced in
1973 [2] and illustrated in Figure 1(a),
replaced more complex latches with a
Digital Object Identifier 10.1109/MSSC.2016.2603228
Date of publication: 14 November 2016

VDD

VDD
X

Logic

Logic
CK

VDD

N
Block

P
Block
Y

(a)
Figure 1: (a) C2MOS logic and (b) an example of single-phase clocking.

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(b)

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