IEEE Solid-State Circuits Magazine - Fall 2016 - 11

The resulting degradation is less serious in Domino due to the restoration
provided by the inverter. Nevertheless, the inverter does draw a static
current in such a case. By contrast,
C2MOS logic is free from charge sharing (why?).
The single-phase clocking of
CMOS latches can be traced back
to 1973, when Oguey and Vittoz reported the scheme shown in Figure
4 for a divide-by-two circuit [6]. Compared to C2MOS, this configuration
employs fewer devices per branch.
In 1974, Piguet filed a patent for the
latch topology depicted in Figure 4(b)
[7], where the clocked device in the
first stage is tied to its output node.
In 1986, Christer Svensson of
Linkoping University, Sweden, having
read the NORA paper [5] and been intrigued by its properties, asked high
Ph.D. student Ingemar Karlsson to
investigate methods of improving its
performance [8]. Karlsson came up
with a different idea and ran some
SPICE simulations that looked promising. Svensson then assigned the
task to his other Ph.D. student, Jiren
Yuan. Yuan modified Karlsson's topology and, in July 1986, reported
his findings to Svensson. Figure 5
shows the TSPC topology drawn by
Yuan in that memo [8].
TSPC gradually found its way into
digital design. In 1992, Digital Equipment Corporation reported the use of
TSPC in its Alpha microprocessor [9].
In 1993, Lu et al. exploited the idea in
the design of a 700-MHz 24-b accumulator [10], and Rogenmoser et al. demonstrated its potential in a 1.16-GHz
prescaler [11].

VDD

N
Block

VDD

Vout

CK
(a)

Figure 2: Domino logic.

VDD

VDD
VDD

CK
CK

N
Block

P
Block

(b)

Figure 3: NORA logic.

Figure 4: (a) A single-phase frequency divider reported by Oguey and Vittoz in 1973
and (b) a latch filed for patent by Piguet
in 1974.

guarantee that, when CK goes low to
precharge the first stage, the second
stage's output remains intact. In summary, when CK is high, the first stage
evaluates while the second senses,
and when CK is low, the first stage is
reset while the second stores.
As an application example, TSPC can
be used in a divide-by-two circuit. Since
the cascade shown in Figure 6(b) does
not invert, we precede it with a third
TSPC stage using a clocked PMOS transistor [Figure 6(c)] and tie the output
to the input [1]. Note that this arrangement exhibits no charge sharing.
It is possible to further reduce the
number of clocked transistors through
the use of "split" outputs [1]. Beginning
with the structure of Figure 6(a) and
recognizing that the drain and source

voltages of M 3 are roughly equal when
CK is high, we follow the stage with an
inverter but split the signal paths [Figure 7(a)] [1]. This latch passes A to X if
CK is high and freezes X if CK is low
and A has no high-to-low transitions.
Since the high level at node B 2 is equal
to VDD - VTH3, transistor M 5 receives
less overdrive and suffers from some
speed degradation.
To arrive at a master-slave flipflop,
we precede the foregoing cascade
with another clocked branch with
split outputs, as shown in Figure 7(b).
This realization incorporates only two
clocked devices, serving as an attractive candidate for large register files. It
is interesting to note that, even though
the first stage is sensitive to input
transitions when CK is high, the overall

TSPC Principles
Let us return to the C2MOS topology of
Figure 1(a) and, in the spirit of Piguet's
circuit, remove one of the clocked
transistors [Figure 6(a)]. When CK is
high, the latch reduces to an inverter
and operates properly. When CK is
low, the circuit is in the store mode
and retains the output state if A does
not change or has only a low-to-high
transition. If we precede this structure with a Domino stage that incorporates N-type logic [Figure 6(b)], we

Figure 5: Yuan's original drawing of a TSPC circuit.

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2016