IEEE Solid-State Circuits Magazine - Fall 2016 - 118

Fs = 4x fLO

RX

Fs = fLO /4
gm

gm

LNTA

4/8 CS
BPF

4/4 CS
BPF

LO
25%

-fs /2

fi fs /2

RFIO

/16

4
2

LO
Driver

gm

/2

8

RX_I
Test_I
Test_Q

fi fs /2

SAR
ADC

gm

9

RX_Q

16

ADPLL
with TDC

Buffer

Class E/F2
DPA

-fs /2

8

4 4
Matching
Network
and
T/R Switch

4/8 CS
BPF

fi fs /2

-fs /2

gm

16

SAR 9
ADC

gm

2

FREF
DCO
(4.1-5.1 GHz)

SPI
TX Modulation
Data (SRAM)

DCO
Buffer

KDCO

ADPLL

Figure 4: A block diagram of the BLE transceiver with single-pin antenna interface.

(b)
Part of Column ADCs
(b)

(c)

Part of Column ADCs

Pixel Array
(a)

Part of Column ADCs
(a)
Part of Column ADCs
(c)

(d)

Figure 5: An image sensor showing the 3-D assembly of the column ADCs and the high-dynamic-range captured image.

computational paradigms presents a
number of challenges and opportunities
to the VLSI community.

118

FA L L 2 0 16

Convolutional neural networks
(CNNs) have emerged as state-of-the-art
classification algorithms for applications

IEEE SOLID-STATE CIRCUITS MAGAZINE

ranging from speech recognition to visual
detection; however, they do not efficiently map to conventional microprocessors.



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2016

IEEE Solid-State Circuits Magazine - Fall 2016 - Cover1
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IEEE Solid-State Circuits Magazine - Fall 2016 - 1
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IEEE Solid-State Circuits Magazine - Fall 2016 - Cover3
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