IEEE Solid-State Circuits Magazine - Fall 2016 - 39

Edith Beigné, Pascal Vivet, Yvain Thonnart,
Jean-Frédéric Christmann, and Fabien Clermidy

Asynchronous
Circuit Designs for
the Internet of Everything

©graphic stock

A methodology for ultralow-power
circuits with GALS architecture

A

synchronous circuits have characteristics that differ significantly from those
of synchronous circuits in terms of their
power and robustness to variations. In
this article, we show how it is possible to
exploit these characteristics to design robust ultralow-power circuits within the scope of the Internet of Everything
(IoE) and with globally asynchronous and locally synchronous (GALS) architectures. More specifically, our aim is to
describe the fundamentals of asynchronous circuit design;
to detail specific methodologies with practical examples of
low-power, asynchronous circuits; and to offer clear guidelines that differentiate the usefulness of an asynchronous
circuit compared to a synchronous one according to different application needs.

Why Asynchronous Circuits?
To start, we need to clearly define what an asynchronous circuit is. While a synchronous circuit acts globally on a clock
Digital Object Identifier 10.1109/MSSC.2016.2573864
Date of publication: 14 November 2016

1943-0582/16©2016IEEE

tick, an asynchronous circuit acts locally and on demand
according to incoming events. Historically, synchronous
circuits have been widely developed to integrate more and
more gates in a single chip. Based on a synchronous clock,
they have demonstrated very high performances over the
past 20 years, following easy scaling. Moreover, research
and development for computer-aided design (CAD) tools
have supported synchronous circuits by improving their
performance through clock-tree optimization, static timing
analysis (STA), physical synthesis, and so forth [1], [2].
Today, however, synchronous circuits encounter
increasing limitations that drastically restrain performance
and complex chip integration. Clock distribution on a large
number of flip-flops is more and more difficult to manage.
Ensuring proper synchronous functionality requires fine
control of clock skew and jitter in very advanced technology nodes. Thus, it is difficult to achieve timing closure
when targeting very high frequencies in complex digital
circuits. Moreover, due to process-voltage-temperature
(PVT) variations encountered by new technologies, large
timing margins are required to increase robustness to
on-chip fluctuations.

IEEE SOLID-STATE CIRCUITS MAGAZINE

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2016

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