IEEE Solid-State Circuits Magazine - Fall 2016 - 65

Basic Operation
An SAR ADC implements a binary
search algorithm to find the digital
code that bests represents the analog input. This algorithm requires
exactly N steps to find an N-b digital
code. An example for a 3-b ADC is
shown in Figure 2, where a given analog input voltage (Vin) is translated
to an output code given a full-scale
signal range between -1 and +1 V.
In the first step, the unknown Vin
is compared to a reference Vref that
is initially set to the middle of the
range (i.e., 0 V in this example). As
shown in the figure, Vin < Vref, so the
first bit is resolved as 0, and the reference is now shifted to the middle
of the remaining search range. Since
we know that Vin must be between -1
and 0 V, the new reference is thus set
to -0.5 V. In the next cycle, Vin > Vref,
so the second resolved bit becomes
1; and, therefore, the reference voltage is now updated to -0.25 V. A last
comparison resolves the third bit,
which is 0, thus resulting in the final
digital code 010.
As one can see, the algorithm
requires three components. First, a
digital-to-analog converter (DAC) is
required to generate a reference voltage Vref that is updated depending
on the bit decisions. Second, a comparator is required to compare Vin to
Vref. Finally, logic is required to time
the various operations and to store
the actually obtained digital code.

1.E+07
1.E+06
1.E+05
P/fs (pJ)

architectures for medium accuracies
between 40 and 70 dB of SNDR. In
terms of speed, SAR ADCs have managed to reach sampling rates of up to
90 GS/s when time interleaved [2]. One
of the reasons SAR ADCs are doing
so well is because they use simple
analog and digital circuits that tend
to scale well and benefit from newer
process technologies. Moreover, the
simple structure often allows operation at reduced supply levels, which
can save additional power. In this article, we will discuss the basic design
aspects of SAR ADCs and give a short
overview of state-of-the-art designs
and future trends.

1.E+04
1.E+03
1.E+02
1.E+01
1.E+00
1.E-01
10 20 30 40 50 60 70 80 90 100 110 120
SNDR (dB)
Pipeline ADCs
Sigma Delta ADCs

Flash and Folding ADCs
SAR ADCs
Other ADCs

Figure 1: An ADC performance benchmark, energy per conversion versus SNDR.

Vin

Analog

0
1
0
Digital
Vref (V)

000

001

010 011
010

-0.75 -0.5 -0.25

100
0

101

0.25

110

0.5

111

0.75

Figure 2: A binary search tree of a 3-b SAR ADC.

Vin - Vref
Analog
Input

Vin
Σ

T&H
+

Logic
-

Vref

N
DAC

Digital
Output

Figure 3: A block diagram of a differential SAR ADC.

In addition, a track and hold (T&H)
is also required to sample and hold
the analog input voltage prior to performing the binary search method.
Figure 3 shows a block diagram of an N-b SAR ADC. In this
case, rather than comparing Vin
against Vref, Vref is subtracted from
Vin first, and the comparator simply determines the sign of Vin - Vref,
which is identical to comparing Vin

against Vref. As we will see later,
the T&H is nothing more than a set
of switches, and the DAC is usually
composed of a switched-capacitor
network, leading to a simple hardware implementation.
A simplified timing diagram of an
SAR ADC is shown in Figure 4. After
sampling the input, the digital bits
1-N are decided one by one. A clock at
the sample rate (fs) controls the T&H

IEEE SOLID-STATE CIRCUITS MAGAZINE

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65
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2016
