IEEE Solid-State Circuits Magazine - Fall 2016 - 68

Mismatch tends to be one of the biggest
concerns in DAC design, and often limits the
linearity that can be achieved with an SAR ADC.
high-frequency input signals. When
Δtclk shows a random (noise-like)
behavior, it is called jitter and will
introduce noise at the output. When
Δtclk is constant, this effect is called
time skew. When combining multiple SAR ADCs in a time-interleaved
structure, variations of time skew
in the various sub-ADCs will lead to
distortion for the overall ADC.
Finally, the T&H can also have
imperfections during the hold mode,
in which the output node should ide-

CLK
Vin

Vin

Voltage (V)

∆ttclk

ally be isolated from the input signal.
However, in modern CMOS nodes in
particular, this is not the case. First
of all, transistors can show leakage,
which implies that there is a resistive
path from the drain to the source
of the transistor that connects Vin
to Vout, even when the transistor is
supposed to be turned off. A second
issue is the capacitive coupling from
drain to source due to C ds capacitance, either from the intrinsic
transistor or from the metal inter-

Vout
∆V
Vout
∆ttclk

Vout

Time (s)

∆Vout =
(a)

∂Vin
∂t

∆tclk

(b)

Figure 8: The effect of jitter and time skew.

VDD

Vin+

4Cu

2Cu

4Cu

2Cu

Vout+

fs
Vin-

b2
VDD

Figure 9: A 3-b differential switched-capacitor DAC including T&H.

fa l l 2 0 16

IEEE SOLID-STATE CIRCUITS MAGAZINE

Vout-

connections. The result of both of
these problems is that Vout could
be disrupted by the input signal,
which can lead to faults in the quantization process. Both these problems tend to become more critical
in scaled technologies as leakages
tend to increase, and capacitive coupling could increase due to reduced
dimensions. Minimizing W/L helps
to reduce both leakage and capacitive coupling. Otherwise, using a
higher threshold voltage device
helps to reduce leakage, and layout
techniques could be used to reduce
or cancel capacitive coupling.
Overall, the T&H can encounter a
variety of problems, while the solutions
are sometimes in contradiction with
each other. As a result, the design in
terms of topology and transistor sizing will be a compromise to balance the
various issues.

DAC
The DAC inside an SAR ADC is usually implemented as a switchedcapacitor network. While there are
many variations, an example using
a charge redistribution DAC with
monotonic switching will be illustrated in this article [5]. Figure 9
shows an example of such a DAC
with 3 b of resolution. The differential topology has a set of binary
scaled capacitors with a unit value
of Cu . The sampling switches on
the left side, controlled by a clock
f s , implement the T&H described
previously. First, it will sample
the input voltage (Vin+, Vin-) onto
the top plates of all the capacitors.
The total capacitance Cs as seen by
the sampling switches is 8Cu per
side. At the moment of sampling,
all of the switches controlled by
the digital signals a 2-0, b 2-0 are
connected to ground. The output
(Vout+, Vout-) is directly connected to
the comparator.
As an example, assume Vdd = 1 V,
Vin+ = 0.6 V, and Vin- = 0.4 V; thus,
the differential input voltage is 0.2 V.
After sampling the input voltage
at the output nodes, the SAR algorithm initiates. First, a comparison

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2016