IEEE Solid-State Circuits Magazine - Fall 2016 - 73

describes a 10-b 1-kS/s SAR ADC
that consumes only 1 nW. Such low
power is achieved by using small
DAC capacitors, an energy efficient
comparator design, manually optimized asynchronous logic, and sub1-V operation. Moreover, the leakage
current is carefully reduced by sizing
and the selection of transistor types.
While pure SAR ADCs had a revival
a few years ago, the trend in the most
recent years is to combine SAR ADCs
with other ADC architectures, leading
to hybrid designs. These hybrids try to
take advantage of the power efficiency
of SAR ADCs while using concepts
from other topologies to overcome
the shortcomings of SAR ADCs. For
instance, we mentioned [2] previously, which uses time interleaving to
increase the speed beyond the capabilities of a single SAR ADC. Other works,
e.g., [20], create a pipelined ADC based
on SAR substages, which also increases
the speed of operation as well as the
resolution. A subranging SAR ADC is
presented in [9] that achieves a stateof-the-art power efficiency of 0.85-fJ/
conversion step at 10-b resolution and
at 200 kS/s. Noise-shaping SAR ADCs
[21] or sigma-delta modulators with an
internal SAR quantizer [22] have been
proposed to increase the precision of
SAR ADCs toward the domain that is
presently dominated by sigma-delta
modulators. Altogether, these hybrid
designs open a whole new field of
opportunities to be explored.

Conclusion
This article has described the basics of
the design of an SAR ADC and discussed
various circuit implementations, the
most critical circuit imperfections, and
design tradeoffs. Modern SAR ADCs
can use relatively simple hardware,
yet a lot of algorithmic and circuitlevel innovations can be applied on top
of that to improve power efficiency,
speed, and accuracy. Besides these
basics, the state of the art was briefly
described and future trends were identified. Noting the rapid improvement in
recent years, we can expect more SARbased approaches with unprecedented
performance in the near future.

References

[1] B. Murmann. (2015). ADC performance
survey 1997-2014. [Online]. Available:
http://web.stanford.edu/~murmann/
adcsurvey.html
[2] L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi, M. Braendli, M. Kossel, T.
Morf, T. M. Andersen, and Y. Leblebici, "A
90-GS/s 8-b 667-mW 64x interleaved SAR
ADC in 32-nm digital SOI CMOS," in Proc.
IEEE Int. Solid-State Circuits Conf., San
Francisco, CA, 2014, pp. 378-379.
[3] T. B. Cho and P. R. Gray, "A 10-b, 20
MSample/s, 35-mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 30, no.
3, pp. 166-172, Mar. 1995.
[4] A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit,
14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits,
vol. 34, no. 5, pp. 599-606, May 1999.
[5] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and
Y.-Z. Lin, "A 10-bit 50-MS/s SAR ADC with
a monotonic capacitor switching procedure," IEEE J. Solid-State Circuits, vol. 45,
no. 4, pp. 731-740, Apr. 2010.
[6] B. P. Ginsburg and A. Chandrakasan, "A
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[7] V. Hariprasath, J. Guerber, S.-H. Lee, and
U.-K. Moon, "Merged capacitor switching
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[8] C.-Y. Liou and C.-C. Hsieh, "A 2.4-to-5.2fJ/
conversion-step 10-b 0.5-to-4MS/s SAR
ADC with charge-average switching DAC in
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Circuits Conf., San Francisco, CA, 2013,
pp. 280-281.
[9] H.-Y. Tai, Y.-S. Hu, H.-W. Chen, and H.-S.
Chen, "A 0.85fJ/conversion-step 10-b 200kS/s subranging SAR ADC in 40-nm CMOS,"
in Proc. IEEE Int. Solid-State Circuits Conf.,
San Francisco, CA, 2014, pp. 196-197.
[10] J. Xu, P. Harpe, J. Pettine, C. Van Hoof,
and R. F. Yazicioglu, "A low power configurable bio-impedance spectroscopy
(BIS) ASIC with simultaneous ECG and
respiration recording functionality," in
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2015, pp. 396-399.
[11] P. Harpe, C. Zhou, Y. Bi, N. van der Meijs,
X. Wang, K. Philips, G. Dolmans, and H. de
Groot, A 26-μW 8-bit 10-MS/s asynchronous SAR ADC for low energy radios,"
IEEE J. Solid-State Circuits, vol. 46, no. 7,
pp. 1585-1595, July 2011.
[12] M. Ding, P. Harpe, Y.-H. Liu, B. Busze, K.
Philips, and H. de Groot, "A 5.5fJ/conv-step
6.4-MS/s 13-b SAR ADC utilizing a redundancy-facilitated background error-detectionand-correction scheme," in Proc. IEEE Int.
Solid-State Circuits Conf., San Francisco,
CA, 2015, pp. 460-461.
[13] P. Harpe, E. Cantatore, and A. van Roermund, "An oversampled 12/14-b SAR
ADC with noise reduction and linearity
enhancements achieving up to 79.1-dB
SNDR," in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, 2014, pp.
194-195.
[14] Y.-S. Shu, L.-T. Kuo, and T.-Y. Lo, "An oversampling SAR ADC with DAC mismatch error shaping achieving 105-dB SFDR and
101-dB SNDR over 1-kHz BW in 55-nm
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458-459.
[15] M. van Elzakker, E. van Tuijl, P. Geraedts,
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[16]

[17]

[18]

[19]

[20]

[21]

[22]

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P. Harpe, G. Dolmans, K. Philips, and H.
de Groot, "A 0.7-V 7-to-10-bit 0-to-2-MS/s
flexible SAR ADC for ultra low-power
wireless sensor nodes," in Proc. Euro.
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pp. 373-376.
P. Harpe, E. Cantatore, and A. van Roermund, "A 10-b/12-b 40-kS/s SAR ADC with
data-driven noise reduction achieving up
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M. Liu, P. Harpe, R. van Dommele, and A.
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Conf., San Francisco, CA, 2015, pp. 278-279.
P. Harpe, H. Gao, R. van Dommele, E.
Cantatore, and A. van Roermund, "21.2 A
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S. Porrazzo, V. N. Manyam; A. Morgado,
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About the Author
Pieter Harpe (P.J.A.Harpe@tue.
nl) received the M.Sc. and Ph.D.
degrees from Eindhoven University
of Technology, The Netherlands, in
2004 and 2010, respectively. He is
currently an assistant professor at
Eindhoven University of Technology, with a main focus on low-power
mixed-signal circuits. He is a coorganizer of the yearly Workshop on
Advances in Analog Circuit Design
and a member of the Technical
Program Committees of the International Solid-State Circuits Conference (ISSCC) and the European
Solid-State Circuits Conference. He
is a Senior Member of the IEEE, a
recipient of the ISSCC 2015 Distinguished Technical Paper Award, and
participates in the IEEE Solid-State
Circuits Society Distinguished Lecturer Program.

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