IEEE Solid-State Circuits Magazine - Fall 2016 - 78

Even though the block diagrams for ET and DP
are identical, the circuit operation underlying
these operating modes is not.
range. This actually makes constant
input drive a bad design practice for
polar modulation.
Thus, a form of dynamic bias is
also desirable for polar modulation.
This is not as critical as the classA bias that must be maintained for
ET for maximum control dynamic
range. Bias here has properties
more like the supply for ET: anything above the minimum will work,
but staying close to the minimum
works best overall.
The opposite is true for the polar
supply voltage value. This value is
extremely critical because it does
set the output signal magnitude and

V_PA: DPS Output Voltage for ET (V)

Figure 8: When the supply voltage
(dashed curve) is very close to the signal
envelope, the transistor is compressed and
the operation is polar. Some offset must
exist due to the finite resistance of the (now)
switching transistor.

0.50
0.45
0.40

therefore contributes significantly
to output signal accuracy. This is
illustrated in Figure 8. Now the timing of the supply variations are also
critical for the same reason. We
come to the conclusion that if timing and value are critical for the
supply voltage waveform, then the
PA operation is actually polar since
this is not consistent with the definition of ET.
Achievable energy efficiency of
polar will always be greater than
that from ET. This also follows from
Figures 2 and 7 because a properly
design switching amplifier will spend
most of its time at the end points of
the power dissipation inverted parabolas that also correspond to transistor minimum power dissipation
contours. Furthermore, because the
knee voltage is not a limit for switching, the PA power dissipation in its ON
state is even lower. If you start with
an ET design and work to improve its
efficiency, you will almost certainly
convert to polar operation, which
must be done with care because
circuit operation changes radically
across this transition.

ET Minimum Profile
Signal Envelope
"Detroughed" Profile

0.35
0.30
0.25
0.20
0.15

Polar
Modulation

0.10

ET-Polar
Transition
Envelope
Tracking
0
0
1
2
3
Linear
Envelope Voltage (V)

0.05

Figure 9: operating the supply voltage profile (long-dashed line curve) at a varying amount
above the signal envelope that decreases with increasing output signal magnitude (as opposed to Figure 4) forces hybrid DPST operation.

FA L L 2 0 16

IEEE SOLID-STATE CIRCUITS MAGAZINE

It is sometimes heard that the ET
technique is "adjusting the amplifier
supply (and drive) to keep the PA in
compression and at peak efficiency,
which is not polar because the input
signal is varying." This actually is
a description of polar operation of
the PA (the transistor must be in
C-mode), so such authors are deluding themselves. If the PA is really
at peak efficiency, then it must be
at power saturation, and any variation of the input signal has no influence on the output signal envelope. I
have also seen claims to apply input
signal predistortion to linearize a
saturated amplifier. This is very
sad to see because any such authors
clearly do not understand either linearization or PA saturation. Further,
we cannot redefine circuit behavior based solely on its input-signal
properties. What the transistor actually does in realizing the port-to-port
transfer functions that we actually
measure is what matters.
Of course, it certainly is possible to
operate a DPST neither in pure ET nor
in pure DP. There is a hybrid operating region between these end points.
Most papers in the present literature
that describe their operation as ET
follow supply voltage profiles such
as the one in Figure 9, which shows
that all of the available PA operating
modes are used. Actual ET operation
is only along a small segment of this
profile. To be accurate and unambiguous, this must be described as a
hybrid DPST operation.
The minimum supply voltage
value, here at 1 V, is indicative that
low-voltage operation of the PA is
being avoided. This could be to stay
out of the amplifier P-mode region
[2], which often is the cause for the
gain collapse observed in many
amplifiers at low supply voltages. It
may also be an indication of amplifier operation in class-RS due to poor
PA design for DPS use. For example,
Figure 4 shows a clear lower bound
to supply voltage at 1 V due to classRS where, in Figure 1, with the same
transistor and proper dynamic bias
the PA supports ET operation with

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2016