IEEE Solid-State Circuits Magazine - Fall 2017 - 113

implementing an as-is model trained
assuming ideal systems. For example, an electroencephalogram-based
arrhythmia detector was presented
that can tolerate about 500 faulty
nodes out of 18,00 nodes with no
significant drop in true positive rate,
whereas conventional approaches
drop from 95+% baseline to under
60% with 30 faulty nodes and to 20%
with 120 faulty nodes. Furthermore,
memory consumption during training was addressed by a resourceaware training algorithm to facilitate
training on the chip.
Verma went on to discuss additional ways machine learning can
interact with ultra-low-power circuit
design. For example, trained weights
in machine-learning algorithms are
usually floating points in softwarebased implementations, while, to
enable ultra-low-power design, an
analog approach is preferred, requiring low precision to keep dynamic
range and power/area under control.
A 4-b weak classifier system called

constrained resolution regression was
presented that can achieve almost
the same accuracy as the full-precision digital version.
Finally, the memory wall bottleneck was tackled for weak classifier
implementation by modifying SRAM
to function both as trained classifier weight storage and as the classification engine itself. The latter part
works by activating all bit cells in
the array with word-line voltages corresponding to the input stimulus, in
a spirit similar to content addressable memory, but mathematically
it is in the form of a mixed-signal
dot-product circuit. By considering
the very limited precision in classifier weights (1 b in this case) and the
imperfect analogue components (a
nonideal digital-to-analog converter
that drives each word line), the proposed system was able to achieve
near 90% accuracy when a conventional system achieved about 92%
accuracy, while saving 113 times the
amount of energy.

Verma presented a new approach
to ultra-low-power circuit design.
By leveraging the data-driven and
robust nature of today's machinelearning algorithms that will be at
the heart of many sensor systems
in the future, new design spaces
are opened up to researchers and
IC designers. Instead of optimizing
the circuit in isolation, cross-layer
optimizations spanning circuit and
algorithm/system/application allow
new circuit design techniques that
are both ultra-low power (e.g., low
precision classifier weights) and yet
robust through data-driven resiliency. Such cross-layer and multidisciplinary approaches breathe
new life into the maturing field of
circuit design, and we hope this can
inspire more hardware researchers to learn about machine learning
and other upstream technologies to
develop holistic systems.

-Jiang Wenyu

SSCS Hong Kong Chapter Hosts a Workshop on High-Performance
Wireless and Optical Communication Transceiver SoC Design

T

The IEEE Solid-State Circuits Society (SSCS) Hong Kong Student Chapter organized a two-day workshop,
"High-Performance Wireless and
Optical Communication Transceiver
SoC Design," on 18-19 August 2017 at
the Hong Kong University of Science
and Technology (HKUST), Hong Kong.
The workshop focused on the latest
trends and challenges in wireless and
optical communication transceiver system-on-chip (SoC) design. A crowd

Digital Object Identifier 10.1109/MSSC.2017.2746171
Date of publication: 16 November 2017

Prof. Sam Palermo shares his research on advanced modeling and design of highperformance ADC-based serial links.

IEEE SOLID-STATE CIRCUITS MAGAZINE

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017
