IEEE Solid-State Circuits Magazine - Fall 2017 - 114

IEEE SSCS HKSC two-day workshop speakers (from left): Prof. C. Patrick Yue, HKSC advisor;
Prof. Sam Palermo, Texas A&M University; Dr. Hirotaka Tamura, Fujitsu Laboratories; and
Prof. Jri Lee, National Taiwan University.

Dr. Hirotaka Tamura takes questions from the workshop participants.

Prof. Jri Lee presents a comprehensive overview of advanced clock and data recovery circuits
for high-speed wireline systems.

114

FA L L 2 0 17

IEEE SOLID-STATE CIRCUITS MAGAZINE

Prof. C. Patrick Yue describes the design
considerations for a 10-Gb/s basebandover-fiber I/Q modulator SoC with
integrated mm-wave power amplifier.

of more than 30 attendees, including research postgraduate students
from HKUST, University of Macau,
and ten representatives of industry
from eTopus Technology, Brite Semiconductor, and Semiconductor Manufacturing International Corporation,
were in attendance. The workshop
featured SSCS Distinguished Lecturers (DL) Prof. Sam Palermo, Texas
A&M University; Dr. Hirotaka Tamura,
Fujitsu Laboratories and IEEE Fellow;
Prof. C. Patrick Yue, HKUST and IEEE
Fellow; and Prof. Jri Lee, National Taiwan University.
Yue, professor and director of
the Optical Wireless Lab and HKUSTQualcomm L ab, HKUST, gave the
welcoming remarks and introduced
Palermo, the first Distinguished
Lecturer (DL), who gave the opening
talk, focusing on advanced modeling and design of high-performance
analog-to-digital converter (ADC)based serial links. He discussed the
statistical modeling framework, lowpower >10GS/s ADC designs, and
novel receiver architectures, which
leverage partial analog equalization
embedded in the ADC. Yue then introduced the second DL, Tamura, who
presented his industrial point of view
on the future of chip-to-chip communications technology. He also discussed the roles of high-bandwidth



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017

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