IEEE Solid-State Circuits Magazine - Fall 2017 - 131

in recent years, my hope is that the
semiconductor industry will continue to attract the next generation
of innovative technologists because
there is much challenging and exciting work ahead of us.

Please Describe the Work
You've Done that Led to You
Receiving This Award
My work during the early 1990s contributed to Intel microprocessor speedperformance through the invention
and implementation of the first fully
integrated phase locked loop (PLL) microprocessor clocking circuit, which
revolutionized the rate of microprocessor clock frequency throughout
the semiconductor industry. This invention was used on all the microprocessor products Intel shipped from 1991 to
the processors being shipped even today.
It was the industry's first complex
analog circuit implemented in a digital
logic complementary metal-oxidesemiconductor (CMOS) process without
requiring the integration of any special
precision elements.
I developed a benchmarking methodology for the cooptimization of
the process definition with circuit
requirements. It involved defining circuits that could identify the transistor
and interconnect technology directions
to improve processor performance. This
benchmarking has been used in each
generation of process technology development since Intel's 0.25-μm CMOS process development and continues even to
the present. Today this cooptimization
methodology is used across the semiconductor industry.
I led a team of circuit designers to
overcome the analog-digital mixedsignal circuit integration challenges
in realizing 10-Gb/s high-speed serial input-output (I/O) circuits on a
processor. It was a significant achievement because these serial I/O circuits

replaced the legacy front side bus I/O
ing circuits on microprocessors are
that had been the mainstay approach
among the most-shipped analog cirfor many generations of prior X86
cuit on IC chips to date.
processors and were also used to inAs a manager of static random-actegrate asynchronous
cess memory design
PCI-express I/O on chip.
a nd a n a log cir c u it
These high-speed sedesign teams, he deYoung received
rial I/Os enabled sigvelop ed a pr o cess
the IEEE Frederik
nificant increases in
development and cirPhilips Award
the performance of
cuit design cooptimi"for leadership
Intel processors.
zation methodology, a
in research and
Since 2010, I have
holistic approach to
development
focused my work on a
optimize the microon circuits and
new challenge, which
processor performance,
processes for the
is to lead a research
process density, and
evolution of mi-
group defining the mayield. This integratcroprocessors."
terials, devices, and
ed methodology has
architecture for the
been a significant conbeyond-CMOS IC techtributor toward the sucnology. These efforts are going to help
cess of Intel microprocessor products
sustain not only Moore's law but also
since 1988. Today this cooptimization
to find the directions to make IC even
methodology is used across the semimore capable and energy efficient.
conductor industry. He lead a design
team that successfully laid the groundIan Young
work for the integration in a logic proIan Young is a senior fellow and director
cess of analog mixed signal high-speed
at Intel Corporation. His current role is
serial I/O circuits such as PCI-express
to lead the Intel research in beyondand Intel Quick Path Interconnect on InCMOS devices and circuits in search
tel microprocessors.
of the new semiconductor logic techHe received the 2009 International
nology for the future energy efficient
Solid-State Circuits Conference's Jack
computing devices. Born in Melbourne,
Raper Award for Outstanding TechAustralia, he received his bachelor's
nology Directions paper. He is a
and master's degrees in electrical
Fellow of the IEEE. He holds 74 issued
engineering from the University of Melpatents in integrated technology
bourne, Australia, and subsequently
and circuits and has published over
received his Ph.D. degree in electrical
120 technical papers. He served as
engineering from University of Califorthe Technical Program Committee
nia, Berkeley.
chair of the 2005 International SolidHe was a lead inventor of the oriState Circuits Conference and was the
ginal Intel microprocessor (PLL)
chair of the 1998 Symposium on VLSI
clocking circuits that drove the perCircuits. He was a guest editor for IEEE
formance of Intel Pentium and Intel
Journal of Solid-State Circuits and IEEE
Core processors from 50 MHz to over
Journal of Selected Topics in Quantum
3 GHz. His innovation contributed to
Electronics. He is currently the editorthe rapid increase in the speed and
in-chief of the new IEEE Journal on
performance of microprocessors
Exploratory Solid-State Computational
through the 1990s while following
Devices and Circuits.
Moore's law scaling. The PLL clock-Abira Sengupta

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