IEEE Solid-State Circuits Magazine - Fall 2017 - 139

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FIGURE 5: An extension of output and input parallel neural engines for ternarization and biasing: (a) mask (M) and bias (B) bits and addend
decode and (b) output/input parallel neural engines.

and 3-D integration technologies, several of which are illustrated in Figure 4.
Several hardware accelerators for
deep neural networks (DNNs) were presented in a Circuits session dedicated
to machine and deep learning. One
of those papers, from Hokkaido University, focused on spatially mapping
binary and ternary DNNs into silicon. It
featured a binary DNN inference accelerator with an array of tightly coupled
SRAM-logic modules. The base architecture was extended by introducing
mask and bias bits, as shown in Figure 5. This versatile implementation
accelerated fully connected, densely
connected, and sparsely connected
DNNs with varying widths and depths.
While fair comparisons between this
work and convolutional neural network accelerators are difficult, the TOPS
of this work outperforms by more than
ten times.

The symposia featured a demo session
for the first time. Conference attendees enjoyed 18 table-top real-time
presentations and the opportunity for
in-depth interaction with authors of outstanding papers from both the Technology and Circuits sessions.
The day after the technical sessions
concluded, the International Forum
on Singularity: Exponential X was held,
cosponsored with the Japan Society for
the Promotion of Science. The focus was
the exchange of insight on future implications of the exponential nature to
Moore's law, even if that growth might
not be linked to silicon in the future.

The forum included key thought leaders from a wide field including Intel,
the University of California, Berkeley,
Rakuten, Yahoo Japan, KAIST, and many
others. The forum will be held again
after next year's symposia.

Social Events
One of the social highlights of the
conference was the joint banquet. Circuits and Technology attendees came
together for food and drink and enjoyed
some traditional Japanese Nihon Buyo
dance entertainment.
In addition to the banquet and demo
sessions, there were several other social

Full Symposia Overlap
The full four-day overlap of the Symposia on Technology and Circuits
resulted in many opportunities for
attendees on both sides to connect and
share with each other. In addition to the
two previously mentioned joint focus
sessions, there were also sessions covering emerging reliability solutions
and advanced assembly techniques.

Conference participants talking to authors at the new demo session.

IEEE SOLID-STATE CIRCUITS MAGAZINE

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017