IEEE Solid-State Circuits Magazine - Fall 2017 - 14

Channel
Response

f
FIGURE 2: Notch in frequency response due
to impedance discontinuity.

Due to the channel imperfections,
each output bit is broadened, exhibiting a tail that interferes with the
next bit(s). Called intersymbol interference (ISI), this phenomenon is
more clearly seen in the impulse
response of the channel [Figure 3(b)].
We observe that the tail values at Tb,
2Tb, etc., (called the "postcursors")
respectively represent the ISI introduced in the next bit, the bit after it,
and so on. In general, energy removal
from a signal's spectrum causes ISI,
whether it occurs as wideband loss

[Figure 1(b)] or as narrowband rejection (Figure 2). We surmise that ISI can
be suppressed if we reconstruct the
tail values and subtract them from the
next bit(s).
Let us implement this idea for
canceling the first postcursor in Figure 3(b). We must delay the present
bit by one bit period, scale this result
by a factor equal to h 1, and subtract
it from the next bit. Figure 4(a) shows
such an arrangement.
If we consider D in as the present bit, D out holds the previous bit
and D F a scaled copy thereof. Thus,
D in-D F is free from the first postc ur sor, whet her it is cr e ated by
wideband loss or impedance discontinuities. With a linear delay element,
this loop is still a "linear" equalizer.
A side effect is that the amplitude
noise at the output is scaled by a factor of h 1 and added to the input data,
degrading the signal-to-noise ratio of
each bit.

Din
Main
Cursor

t

Dout

t
Dout

t
(a)

h1

Dispersive
Channel

t

h0 Postcursors
h2

0 Tb 2Tb

t

(b)

FIGURE 3: (a) Random data viewed as superposition of steps and (b) the impulse response of
a lossy channel.

Design Issues

Slicer
Din

+

Tb
-

Dout

Din

Tb

+
-

h1
DF

DF

+

-

(b)
FF

Summer
Din

Dout

h1

(a)

Dsum

D Q

h1

Din
Dout

t

Dsum

CK

t

Dout

DF
(c)

(d)

t

FIGURE 4: (a) A feedback loop canceling the first postcursor, (b) the addition of a slicer to
suppress amplitude noise, (c) the use of an FF as a delay element and a slicer, and (d) the
resulting waveforms.

14

FA L L 2 0 17

IEEE SOLID-STATE CIRCUITS MAGAZINE

This issue can be remedied if
the delay element is followed by a
limiter, also known as a "slicer," so
as to remove the amplitude noise
[Figure  4(b)]. The loop thus stops
the noise from circulating and acts as
a nonlinear equalizer. For robust operation, we replace the delay stage
and the slicer with a f lipf lop ( F F )
[Figure  4(c)], recognizing that typical FFs provide both a one-period
delay and limiting action on the amplitude. We can say the loop feeds the
FF's decision back to the input, hence
the term DFE. As illustrated in Figure 4(d), the summer output, D sum,
is free from the first postcursor, making greater voltage excursions with
less jitter and allowing better de tection. Sensed by the flipflop, this
output is the most critical node in
the circuit.
In the DFE loop of Figure 4(c), two
parameters must be adjusted to reach
optimum performance. First, the clock
sampling edges must occur at the
peaks of D sum, necessitating a clock
recovery circuit. Second, the first "tap"
value, h 1, must be chosen according
to the actual channel response. This
is typically accomplished by monitoring the eye diagram at the summer
output and adjusting h 1 to maximize
its height.
Higher-order postcursors can
also be removed by a DFE. Depicted
in Figure 5, a two-tap realization
returns scaled copies of the last two
bits to the input.

In addition to clock phase alignment
and proper setting of the feedback
tap, the DFE shown in Figure 4(c) must
also deal with the total loop delay.
We predict that, at a sufficiently high
data and clock rate, the circuit begins
to incur errors.
To study the DFE speed limitations,
consider the differential topology in
Figure 6 and suppose the slave latch
in the FF enters the sense mode on
the falling edge of the clock, at t = t 1 .
The slave output requires a certain
amount of time to change state, called
the "clock-to-Q" delay, TCK - Q = t 2 - t 1 .
This transition propagates through
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017
