IEEE Solid-State Circuits Magazine - Fall 2017 - 16

DFE Variants

FA L L 2 0 17

CK1/2

CK1/2
Deven Din

D Q
-

Din

D Q
-

h1
+

D Q

-
Dodd

D Q

Deven

MUX

A multitude of DFE architectures have
been proposed to ease the design
tradeoffs. We study some here.
It is possible to transform the
feedback loop of Figure 4(c) to a predictive or "unrolled" topology. Suppose D in and D out swing between -1
and +1. Since we wish to compute
D in - h 1 D out, we can equivalently
consider D in - h 1 and D in + h 1 as the
only two possible levels that must
reach the FF. The selection between
these two values can be made by
the previous bit. Figure 7 shows the
resulting "unrolled DFE" [3]. Here,
the previous bit available at D out
decides whether D in - h 1 or D in + h 1
must travel through the multiplexer
and be sliced by the FF. We note that
the summing nodes lie outside the
feedback loop, which is the principal advantage of this arrangement.
The timing budget is now given by
TCK - Q + Tsetup + TMUX 1 Tb, where TMUX
denotes the delay from the select
input of the multiplexer to its output. In some cases, TMUX is less than
TFB in (1). However, the D out signal
must be level shifted and/or amplified to properly switch the multiplexer, leading to additional delay.
At very high speeds, it is desirable to drive the DFE with a halfrate clock, CK 1/2, which is simpler
to generate and distribute. Figure 8(a) shows a half-rate DFE [4],
where the FFs are clocked by CK 1/2
and CK 1/2, thereby demultiplexing
the data by a factor of two. Each output bit lasts for 2Tb seconds and,
after subtraction from D in, is fed
to the FF in the other branch. This
topology nonetheless does not relax
the loop timing budget given by
(1). It also consumes about twice as
much power as the full-rate DFE of
Figure 4(c).
Another half-rate DFE architecture
is depicted in Figure 8(b) [5]. Here,
the half-rate outputs are multiplexed
so as to reconstruct the full-rate data,
with the result serving as the feedback signal. While using only one
summer, this method adds the multiplexer delay to TCK - Q + TFB + Tsetup,
degrading the speed.

Dodd

CK1/2

CK1/2
(a)

(b)

FIGURE 8: Half-rate DFE architectures with (a) two summers and (b) one summer and one
multiplexer.

I2
X

Vin1

M1
CK

Y
Vr 1

MCK1

Vr 2

M3
CK

Vin2

MCK2

FIGURE 9: A comparator input stage based on two differential pairs.

At very high speeds, the summing node and the FFs can incorporate inductive peaking for a greater
bandwidth and a smaller loop delay.
This improvement comes at the cost
of a more complex layout and signal
distribution difficulties.

Questions for the Reader
1) Can the delay stage and the slicer
in Figure 4(b) be realized as a single limiting differential pair?
2) Can the unrolled DFE of Figure 7
accommodate a second tap?

Answers to Last Issue's Questions
1) In Figure 9, why can we not apply
Vin1 and Vin2 to M 1 and M 2 and
Vr1 and Vr2 to M 3 and M 4 ?
In such a case, each differential
pair can experience a large input
difference even when the comparator is making a critical decision.

IEEE SOLID-STATE CIRCUITS MAGAZINE

As a result, the transconductance
of the two pairs falls considerably,
making the offsets of the subsequent stages significant.
2) How does the characteristic shown
i n Fig u r e 10 ( b) c h a nge i f the
front-end comparator has an offset equal to 1.5 least-significant
bits (LSBs)?
In the ideal case, we have
V +F - V -F = V +in - V -in if V +in - V -in 2 0
a n d V +F - V -F = - (V +in - V -in) i f
V +in - V -in 1 0. With a comparator offset of 1.5 LSBs, the former
holds if V +in - V -in 2 1.5 LSBs and
the latter, if V +in - V -in 1 1.5 LSBs.
That is, the circuit negates the
differential input even for values
reaching = 1.5 LSBs. The resulting characteristic is shown in
Figure 10(c).
(continued on p. 132)

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