Andreia Cathelin T he race on the C o m plement a r y Metal-Oxide-Semiconductor (CMOS) More Moore integrat ion sc a le h a s br oug ht to light several major limitations for efficient planar process integration starting with the 40 nm technology node. The transistor channel was more and more difficult to control in terms of electrostatics, and many process engineering methods (such as, for example, Silicon strain) were used to provide transistors with good carrier speed and decent electrical characteristics. Starting from the 28-nm node, the obvious solution for transistors with increased electrical performances was the use of fully depleted devices. Two integration methods have been identified by the semiconductor industry for these fully depleted devices: Fully Depleted Silicon on Insulator (FD-SOI) CMOS and FinFET CMOS devices. While the fundamental carrier semiconductor equations are similar, the process integration is very different. This a r t icle fo c uses on pla n a r F D SOI CMOS technology features as integrated by STMicroelectronics Fully Depleted Silicon on Insulator Devices CMOS The 28-nm node is the perfect technology for analog, RF, mmW, and mixed-signal system-on-chip integration Digital Object Identifier 10.1109/MSSC.2017.2745738 Date of publication: 16 November 2017 18 FA L L 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/17©2017IEEE