IEEE Solid-State Circuits Magazine - Fall 2017 - 19

in the 28-nm node [1], [2], and
its specificities for analog, radio
frequency (RF), millimeter wave
(mmW), and mixed signal systemon-chip (SoC) integration.
Figure 1 is a generic cross section of an FD-SOI CMOS device.
This technology is called UltraThin Body and Buried Oxide
(UTBB) FD-SOI CMOS as, in the
28-nm node, the active device
has a ultra-thin conduction film
(7 nm) and lays atop a 25-nm
insulation layer of buried oxide
(BOX). This planar topology has
the following direct implications.
Thanks to the SOI BOX layer, the
transistor gets total dielectric
isolation. No channel doping is
needed as, thanks to the thin
silicon film, the channel is fully
depleted. Also enabled by this
technology, no pocket implants
are needed for the source and
drain, which naturally enhances
the analog/RF transistor's behavior. Another implication of the
thin BOX layer is that the frontside transistor's electrostatics
can be controlled from underneath the BOX (an area called the
transistor body). By applying a
voltage on the transistor body,
one can change or modulate the
threshold voltage of the main
(front side) transistor. We can see this
device as well as a planar dual-gate
device: the front gate is the regular
one (like in bulk technology) and the
second one comes from the body tie,
with the BOX as the back-side gate
oxide. As the thickness ratio of the
front and back gate oxides is about
ten, the front-side transistor's transconductance Gm is ten times bigger
than the one on the back-side gate.
In terms of manufacturing, the
28-nm FD-SOI CMOS process from
STMicroelectronics shares most of
process steps with the equivalent
28-nm bulk technology from STMicroelectronics. It is a modified bulk

28-nm high-K metal gate low-power
(LP) process using the same back end
of the line and gate module. Several
process steps, specifically channel
implants, halo implants, and masking levels, are removed compared to
the traditional 28-nm bulk technology thanks to the presence of the
undoped FD-SOI channel. There is
less than a 20% change with respect
to a classical CMOS bulk flow; the two
extra steps are related to the hybridization and raised source/drain epitaxy. At this node, more than 10% of
the process steps and seven masks
are saved, resulting in an overall manufacturing process cost saving of
10% [3]. This process offers the efficiency of fully depleted devices along
with the manufacturing yield of planar technologies.

FD-SOI Devices and Body Biasing
Opportunities
For good understanding of the specific features of different FD-SOI
transistors, let's first start with a
small reminder from planar bulk
CMOS transistors.

Figure 2 is a cross section of
N - type MOS (NMOS) and P-type MOS
(PMOS) transistors in a regular bulk
CMOS technology. A threshold voltage
(VT ) modulation can be obtained by
body bias tuning (VBBN and VBBP).
This is very limited by the threshold voltage of the parasitic source/
drain diodes toward the respective
transistor body. As this voltage is about
0.6 V, the effective safe body-biasing
(BB) voltage range spans from 0 to
~ 0.3 V (modulus). The body factor
in bulk technologies is also quite limited (25 mV/V); hence the total possible
variation of the threshold voltage is
limited in bulk technologies to only a
few tens of millivolts.
Fig u r e 3 pr e s e nt s c r o s s s e ctions of the NMOS and PMOS transistors in the 28-nm UTBB FD-SOI
technology. The darker side of the
N-wells corresponds to the deep-Nwell layer.
Regarding the regular VT (RVT)
transistors [see Figure 3(b)], one can
observe the specific UTBB FD-SOI
topology, with the raised sources and
drains and the thin BOX isolating

FBB
Gate

Source
Drain
Ultra-Thin Buried Oxide

Total Dielectric Isolation

No Channel Doping

No Pocket Implant

FIGURE 1: A generic cross section of an UTBB FD-SOI transistor.

IEEE SOLID-STATE CIRCUITS MAGAZINE

FA L L 2 0 17

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017