IEEE Solid-State Circuits Magazine - Fall 2017 - 20
Starting from the 28-nm node, the obvious
solution for transistors with increased
electrical performances was the use
of fully depleted devices.
the front-side transistor from its
body. In this case, for VT modulation through body biasing, the only
limiting parasitic diodes are those
between deep N-well to P-substrate
for NMOS and respectively embedded P-well to deep N-well for PMOS
devices. These are Zener-type diodes,
with an opening voltage around
modulus of 3 V. Hence, we can do a
NMOS
PMOS
G
G
S
VBBN
D
S
D
VBBP
N-Well
P-Well
P-Sub
FIGURE 2: A cross section of CMOS transistors in a regular bulk technology.
VBBN
NMOS
PMOS
G
G
S
D
S
D
Box
Nominal
VBB
VBBP
LVT
NMOS
Box
GND
P-Sub
VBBP
S
D
VBBN
RVT
PMOS
Box
FBB
+0.3
3
RBB
VDD
-3
P-Well
N-Well
RVT
NMOS
P-Sub
-3
FIGURE 3: A cross section of 28-nm UTBB FD-SOI CMOS transistors: (a) LVT transistors and (b) RVT transistors.
IEEE SOLID-STATE CIRCUITS MAGAZINE
VDD/2 -0.3
3
RBB
GND
(b)
FA L L 2 0 17
3
G
S
Box
20
-0.3
-3
(a)
NMOS
G
D
FBB
-3
LVT
PMOS
PMOS
Biasing Mode
GND
P-Well
N-Well
very efficient body biasing on these
RVT devices, called here reverse body
biasing (RBB), with the effective biasing voltage range from roughly 0 to
3 V (modulus).
Let's now focus on the low VT
(LVT) devices, as depicted on the
upper part of Fig ure 3(a). These
devices are also called "flippedwell" devices, as in order to obtain
the lower VT characteristics, the
process engineering has proposed
a solution where the NMOS devices
lay on an NWell body, and respectively the PMOS on a PWell body.
In an equivalent way, we can apply
forward body biasing (FBB) on these
devices, with also an equivalent
body voltage variation from roughly
0 V to 3 V (modulus).
The body factor for both families
of transistors (RVT and LVT) is much
larger in FD-SOI than in an equivalent body node, in 28 nm being
~85 mV/V, for the thin oxide devices.
This argument together with the
very wide body biasing range result
VDD/2 +0.3
3
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