IEEE Solid-State Circuits Magazine - Fall 2017 - 21

in an unprecedented wide variation
of the threshold voltage of around
250 mV, as depicted in Figure 4.

0.6

RBB

0.4

When we were following the historical nanometer downscaling of
the CMOS bulk road map, the analog designers had to get used to the
fact that the analog behavior of the
respective transistors was getting
worse and worse with the downscaled technology node. This was
inherent from the planar CMOS bulk
transistor topology, in the race for
faster and faster digital behavior
and/or low power. Some foundries,
like STMicroelectronics, had overcome that in the 65-nm node by
introducing a specific analog transistor called HPA (high performance
analog) that solved this by eliminating the transistor pockets. In the
28-nm FD-SOI planar technology,
thanks to the thin film structure, we

1E+3

FBB

0.0
FBB

-0.2

RBB

-0.4
-0.6

-3

-2

-1

0
1
VB (V)

2

3

FIGURE 4: The threshold voltage (VT) variation with respect to BB voltage for RVT and LVT
devices in 28-nm FD-SOI technology.

do not need transistor pockets, and
we recover native analog behavior
from a "simple" and well-controlled
fully depleted conduction channel.
FD-SOI hence brings several advantages for analog designers in
terms of efficient short-channel
devices, improved analog performances, and lower noise variability.

In Figures 5-7, we compare the 28-nm
FD-SOI technology with an equivalent 28-nm node LP bulk technology,
both from STMicroelectronics.
Figure 5 shows major improvements of FD-SOI versus bulk solution regarding analog gain and VT
matching parameter. For example, in
28-nm FD-SOI, an LVT NMOS device

5.0

dc Gain-Lin (Gm/Gds)

28LP Bulk

Avt (mV.µm)
4.5 Curves for W = 1 µm
4.0

28FDSOI

1E+2

3.5

28LP Bulk

28FDSOI

3.0

1E+1

1E+0
1E-8

NLVT
NRVT
PLVT
PRVT

0.2

Vth (V)

FD-SOI Transistors
Analog Features

2.5
2.0

Gate Length (m)
1E-7

1E-6

1.5
1E-8

1E-5

Gate Length (m)
1E-7

(a)

1E-6

1E-5

(b)

FIGURE 5: (a) Analog gain (Gm/Gds) and (b) matching parameter (Avt) for NMOS LVT devices in 28-nm FD-SOI technology (red) compared
with 28-nm LP bulk (blue).

21
20 Gm/ld (1/V)
19
18
17
16
15
14
13
12
11
1E-8

140

28FDSOI

120

Cgg (fF/µm)

28LP Bulk
28FDSOI

100

28LP Bulk

80
60
40

Gate Length (m)
1E-7

(a)

1E-6

1E-5

20
0
1E-8

Gate Length (m)
1E-7

(b)

1E-6

1E-5

FIGURE 6: Improved analog performance (Gm/Id and total gate capacitance Cgg) for NMOS LVT devices in 28-nm FD-SOI technology (red)
compared with 28-nm LP bulk (blue).

IEEE SOLID-STATE CIRCUITS MAGAZINE

FA L L 2 0 17

21



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017

IEEE Solid-State Circuits Magazine - Fall 2017 - Cover1
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IEEE Solid-State Circuits Magazine - Fall 2017 - 1
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