IEEE Solid-State Circuits Magazine - Fall 2017 - 22

Noise_Sv at Hz (V/√Hz)

3.0E-5

ure 7. As an example, for an LVT NMOS
of 1 nm/120 nm bi a s e d at a 1 nA
drain current, we get 1.5 dB lower 1/f
noise in an FD-SOI than in bulk. This is
a typical value of main branch current
for a low-noise amplifier in low gigahertz frequencies.

FD-SOI Transistors
RF and mmW Features
Thanks to the deep submicron lithography, this technology node
provides very fast transistors. The
intrinsic devices [front end-of-line
(FEOL) plus Metal1 contact] in the
LVT flavor, for example here NMOS,
show fT and fmax superior to 300 GHz.
(See Figure 8.)
We can distinguish two types of
dimensioning and biasing strategies,
depending on the operation frequency.

Input Ref. Voltage Noise at 1 Hz
for NLVT W = 1 µm/L = 1 µm

2.5E-5
2.0E-5
1.5E-5

28LP Bulk

1.0E-5

28FDSOI
Idrain/W (µA /µm)

5.0E-6
1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2
(a)

Noise_Sv at Hz (V/√Hz)

of a size 1 nm/100 nm can show an
excellent analog performance with
a DC gain of 80 and a sigma(VT ) of
only 6 mV.
Figure 6 shows that FD-SOI provides a higher Gm for a given current,
with respect to the equivalent 28-nm
LP bulk node. This, combined with
the lower parasitic capacitances coming inherently from the SOI insulation, permits the designer to achieve
higher operation bandwidths for a
given current consumption, or -if
working at constant bandwidth-lower
power consumption.
The variability in planar FD-SOI
technologies is improved with re spect to an equivalent LP bulk node,
thanks to the simpler manufacturing
process steps. This helps as well for
the noise behavior, as is shown in Fig-

If we talk about RF operation frequency
below 10 GHz, we can then work with a
transistor length of 100 nm. Performances such as a maximum available
gain (MAG) of 12 dB and NFmin of approximately 0.5 dB can be obtained for
a current density 125 nA/nm (here
W = 1 nm). Going higher in frequency
will then require working with the
minimum transistor length of 30 nm.
Here, for example, for a 60-GHz operation frequency, a MAG of 12 dB and
NFmin of approximately 1.3 dB can be
obtained, when working at a current
density of 200 nA/nm. This value is
33% lower than in 28-nm LP CMOS bulk.
In a fully integrated schematic, all
back end-of-line (BEOL) layers have to
be added atop the intrinsic transistor
to withstand the respective current
biasing conditions, respect the metal

1E-4
Input Ref. Voltage Noise at 1 Hz
9E-5 for NLVT W = 1 µm/L = 120 nm
8E-5
7E-5
6E-5
5E-5
28LP Bulk

4E-5

28FDSOI
3E-5
Idrain/W (µA /µm)
2E-5
1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3
(b)

400

400

300

300

fmax Meas [E+9]

fT Meas [E+9]

FIGURE 7: Noise behavior for NMOS LVT devices in 28-nm FD-SOI technology (red) compared with 28-nm LP bulk (blue).

200
100
0
0.0
fT

0.2

0.4
0.6
0.8
1.0
vgs [E+0]
Versus vgs (Model = LVTNFET WFING = 5e-07
vds = 1 L = 3e-08)
(a)

200
100
0
0.0

0.2

0.4
0.6
0.8
1.0
vgs [E+0]
fmax Versus vgs (Model = LVTNFET WFING = 5e-07
vds = 1 L = 3e-08)
(b)

FIGURE 8: The high-frequency behavior (fT and fmax) of LVT NMOS 0.5 μm/30 nm in 28-nm FD-SOI CMOS.

22

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