IEEE Solid-State Circuits Magazine - Fall 2017 - 23

Cross Section

Drain
Source

Drain

Gate

35
30
25
20
15
10
5
0
-5
Gate -10
1E10

Source

Top View

fmax
-20 dB/dec
m4 m2

H21
1E11

1E12

Frequency (Hz)
(b)

(a)

FIGURE 9: Full ten metal layers BEOL implementation of an NLVT transistor of 16 µm/30 nm, Wfinger = 800 nm for a drain current of
5.2 mA. The initial design kit Pcell stops at Metal 1. Measurements are performed on 10-110 GHz and, respectively, 220-330 GHz test
benches independently.

550
500

28FDSOI

450
Vth (mV)

density rules, and fulfill the electromigration current density rules up to
a maximum operation temperature.
At the same time, the designers have
to take great care in minimizing the
full BEOL effects on the effective fT
and fmax degradation. An example of
implementation is given in Figure 9(a)
for a transistor in a mmW oscillator
core, where thin staircase accesses
for low fringe parasitic capacitors
between drain and source have been
implemented, and the gate access
resistance is optimized through a
dual gate access [4]. On-wafer deembedded measurements of this
device showed that such a full BEOL
transistor still sustains a very good
mmW performance: fT of 246 GHz
and fmax of 359 GHz, as depicted in
Figure 9(b).
Deep submicron CMOS has the
counterpart of very low and dense
BEOL, with a large number of metal
layers. While this might be seen as
a limiting point for mmW design,
the eight metal layers of this technology obtain decent values for the
integrated passive devices. This is
enabled by the operation in a low
parasitics environment coming with
the SOI technologies. Several examples can be cited here: an inductor
of L = 0.5 nH with a Q factor of 18 at
10 GHz, a varactor of C = 50 fF with a
Q factor of 20 at 20 GHz, and a 50-Ω
transmission line of 0.8 dB/mm losses
at 60 GHz.

Slow
Typ
Fast

400
350
300
250
200

Slow
Typ
Fast

28LP Bulk

150
1E-8

1E-7
1E-6
Gate Length (m)

1E-5

FIGURE 10: VT process corners for LVT NMOS devices, comparing a 28-nm FD-SOI CMOS and
28-nm LP bulk.

FD-SOI Transistors
Mixed Signal Features
In terms of process variability, we
experience tighter process corners
and less random mismatch in FDSOI than in competing processes at
the same lithography node. The benefits become obvious in terms of a
simpler design process and shorter
design cycle, leading to improved
yield or improved performance at
given yield. Figure 10 illustrates this
for the VT parameter.
Reduced VT from body biasing
has also excellent i mpl ic at ion s
for CMOS switches (pass-gates), as
depicted in Figure 11 [5], resulting in an unprecedented quality of
analog switches. One can observe
the exceptional flat behavior of the
CMOS switch resistance in the case
of the FD-SOI integration using body

biasing, its absolute value being much
lower than the one in bulk. We experience here compounding benefits:
a smaller resistance yields a smaller
switch with a more compact layout,
hence with lower parasitics, which
finally gives an even smaller switch.
This feature is key for high-performance data converters and other
switched-capacitor circuits.
Lower junction capacitances as
those experienced in FD-SOI make
a substantial difference in high-speed
circuits. They permit drastic reduction of self-loading in gain stages and
a significant reduction of switches
self-loading. This yields a two-fold
benefit: not only incremental improvements, but mostly they allow the
designer to use circuit architectures
that would be infeasible/inefficient
in bulk technologies [6].

IEEE SOLID-STATE CIRCUITS MAGAZINE

FA L L 2 0 17

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017