Computing Subsystem (HW) DET CPU0 CPU1 DET CPU0 TEMP TEMP Performance-Driven CPU Cluster Shader0 Shader1 Energy-Efficient CPU Cluster System Power Manager Power-Efficient GPU Cluster Vdd PTP Controller PMIC 45 80 70 40 Power Savings (Typ) (%) PTP: +23% GHz 60 50 40 30 20 10 0 CPU1 PTP: -30% Power (avg) 35 30 25 20 15 10 5 90 100 110 120 (%) 130 GHz 140 0 Fast Typ Slow Silicon Speed 30 130 25 110 20 90 15 70 10 50 5 30 0 Time Temperature (C) Average Power Saving (%) FIGURE 1: PTP detectors enable adaptive voltage scaling for optimal power/performance of the CPU complex. With Temperature Monitoring Without Temperature Monitoring Temperature 10 FIGURE 2: Temperature monitors allow for additional power savings across time as the temperature fluctuates. at the lowest voltage that still guaran- tees speed and quality [1]. The goal of adaptive techniques is to maximize performance while 28 FA L L 2 0 17 staying below the thermal budget of the chip, as shown in Figure 1. Power, thermal, and performance (PTP) detectors are distributed within IEEE SOLID-STATE CIRCUITS MAGAZINE the CPU to detect when operating conditions have changed. This ad - aptive technology allows the device to use available voltage margin to boost performance or lower power consumption when possible. A small controller monitors the detector data dynamically trimming the device for dc voltage bias, aging, and tempe- rature adjustment as the device is exposed to different conditions. The result is 20% megahertz boost or 30% power savings depending on the sys- tem-on-chip (SoC) operating condition. Figure 2 shows the power savings over time due to the temperature sensors. Adjusting the voltage with tempera- ture can save an additional 5-10% of power. The technology is IP agnostic, thus all processors and digital logic in the SoC are able to gain a similar power savings benefit.