Using back-gate biasing is another way to adaptively adjust the silicon for process variation. Forward-body bias (FBB) increases the performance of slow silicon by applying 400 mV to the body of the P-type metal-oxide- semiconductor transistors in a 28-nm process node CPU. The body-bias switch is integrated into the distrib- uted power switch to ensure even distribution of all relevant voltages across the CPU (Figure 3). A careful power sequence of the voltage rails is needed to prevent short circuit current between supplies [2]. Adaptive power allocation is used to maximize CPU performance within the currently allocated power bud- get by instantly reallocating power from low-activity CPUs to high-activ- ity ones, thus avoiding performance throttling on high-activity CPUs. In scenarios where the cumulative power of all CPUs exceeds the total clus- ter budget, automatic clock gating is introduced as a temporary coun- termeasure and is achieved by clock The goal of adaptive techniques is to maximize performance while staying below the thermal budget of the chip. dithering. When clock dithering is active, a secondary process adjusts the on-chip phase-locked loop fre- quency and off-chip dc-to-dc converter voltage to a more energy-efficient oper- ating point to maximize performance. The control loop goes between clock dithering and voltage/frequency ad- justment to achieve maximum per- formance, which occurs when total power consumption is close to the power budget. A two-times performan- ce improvement is observed when power is limited to 25% of normal operating power [3]. Sipping Power Through a Straw (Power Delivery Network) Powering the processors is also a very important consideration, and the design of the power delivery network (PDN) impacts the perfor- mance capability. Because a very robust PDN is also associated with a higher cost, there is a very care- ful tradeoff between the cost of the PDN solution versus the performance achievable by the processor that needs to be considered. During run time, the processors switch between light and heav y work loads continuously, causing voltage droop in the PDN. These droops diminish the voltage margin available and compromise CPU oper- ating speed. To minimize voltage droops, a remote-sensing technol- ogy is employed [1]. A feedback line using a printed circuit board (PCB) trace to a location closest to CPU power pins provides actual CPU volt- ages to the power management IC VNWBIAS RVDD PDB VDDB VDD RET ORET BIASEN OBIASEN OPDB RVDD VNWBIAS PDB Power-Up Active Retention Active Retention Transition Transition Transition FBB Transition No FBB Transition BIASEN Transition RET No FBB Active FIGURE 3: A hybrid switch to support body biasing and power sequencing required to prevent short circuit current between supplies. IEEE SOLID-STATE CIRCUITS MAGAZINE FA L L 2 0 17 29