IEEE Solid-State Circuits Magazine - Fall 2017 - 30

PKG

Die

PCB

VCC
Pkg Cap

VCC
Max

VCC
Max

VCC

VCC

Min

PCB Cap
PMIC

Min
Remote Sensing Off

Remote Sensing On

FIGURE 4: Oscilloscope plots of voltage measured at the probe location on the PCB closest
to the IC before and after remote sense (VCCmax and VCCmin are the high and low voltage
specs, respectively).

Without Clock Gating Second Droop: 118 mV

With Clock Gating Second Droop: 64 mV

FIGURE 5: A silicon measurement of WFI ➔ max-power showing droop reduction from
118 to 64 mV of the second droop through aggressive clock gating when the transient is
detected. WFI: wait for interrupt.

Bandgap
Voltage

Reference
Voltage
Generator

2.5-GHz Clock
Voltage
Monitor Array
VMon0
VMon1
VMon2
VMon3
VMon4

1.8 V Supply
State

Digital
Control

Activation
Code
Response Time <1 ns
DIE_SENSE_VDD
DIE_SENSE_VSS

FIGURE 6: Droop mitigation design with response time <1 ns.

30

FA L L 2 0 17

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IEEE SOLID-STATE CIRCUITS MAGAZINE

Power
Switch
Array

CPU
Cluster

(PMIC). The voltage delivered from
the PMIC continuously compensates
for any losses, thus power deliv-
ered to the processors is guarante-
ed to within a known error margin.
The feedback mechanism is con-
tinuous, and thus power supplied
is constantly tracked and adjusted
during operation. Figure 4 shows
oscilloscope plots before and after
remote sense are enabled achiev ing
18 mV(dc), 11 mV(ac) power sup p -
ly compensation.
Increasing CPU clock frequency,
core count, and lower supply voltage
stresses both the power distribution
network and the dc/dc converter from
current load transients. Aggressive
clock gating in a high-performance
CPU creates an additional challenge:
idle CPUs enter an idle state in which
dynamic power is completely elimi-
nated, and consequently the dc/dc
converter switches from pulsewidth
mode (PWM) to pulse-frequency mode
(PFM). When this event is detected, the
CPU clocks are automatically switched
to a lower clock frequency, thus pre-
venting a large step in supply current
and minimizing the dI/dt transient.
Without this feature enabled, the
maximum VDD droops 118 mV, as
the dc/dc converter transitions from
PWM to PFM. When enabled, the droop
is reduced to 64 mV due to lower ini-
tial current demand, achieving a 45%
reduction in VDD droop (Figure 5) [2].
Another droop reduction scheme uses
a 1.8 V supply to deliver momentary
boosting current and charge to the
CPU (Figure 6). A bank of five clocked
on-die voltage sensors continuously
monitors the internal power supply
voltage, using an externally supplied
2.5-GHz clock. State-based logic, in
turn, monitors the five sensor outputs
and, upon detecting a droop occur-
rence, sends a 12-b activation code to
the integrated bank of power switches.
This switch activation effectively can-
cels the resonant droop before it
reaches the minimum voltage, thus
improving VMIN. For effective droop
reduction, the entire process from
detection to prevention must occur in
under 1 ns [4].
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017
