IEEE Solid-State Circuits Magazine - Fall 2017 - 31

A structured clock mesh is often used in
high clock rate CPUs to minimize clock
insertion delay and end point skew. In
the CPU, a "fishbone" structure is con-
structed to propagate the main clock
to a grid of 229 tap-points across the
CPU. As shown in Figure 7, the fishbone
utilizes a distributed driver column
tied to horizontal spines; no additional
vertical strapping is used, eliminating
half of the traditional mesh capacitance.
The resistance-capacitance (RC) of each
spine is constrained by using tap-point
buffers at each grid point, minimizing
capacitance and RC variation of each
spine. Traditional clock tree synthe-
sis (CTS) is used to connect from the
tap-points to lower-level gates, allowing
skew to be used as required [2].
A direct connection to a large num-
ber of clock tree elements maximizes
the potential benefit of a mesh style of
clock grid. To achieve this, the first
level of functional clock gates instan-
tiated in the register transfer level are
logically combined into the second
level. This increases the number of
first-level clock loads from three to
3,009, which are immediately behind
229 tap-point buffers. The overall CPU
clock insertion delay is reduced by 35%
while maintaining parity power with
traditional CTS in a 28-nm CPU design.

How to Lay a Good Foundation
(Standard Cell and Embedded SRAM)
Once the CPU specification and micro-
architecture are defined, the next
step is to implement them into digital
logic and implement the place and
route. One knob for additional tuning
of the power/performance of the CPU
is the standard cells and embedded
memory (SRAM) design to achieve the
power/performance target.
To meet CPU L1 cache SRAM perfor-
mance requirements while minimiz-
ing the power consumption, three
design options were explored: 1) high-
density (HD) versus high-current (HC)
bit cell, 2) 64 b/bit line (bbl) versus
32 bbl, and standard threshold volt-
age (VT) versus low VT periphery
transistors. Figure 8 shows the design

CPU Bounding Box
Fishbone "Spine"
Fishbone "Ribs"
Tap-Point Buffer
First-Level Clock Gate

FIGURE 7: A fishbone clock physical structure.

200
HD

HC

64 b/bl

32 b/bl

175
SVT
Reactive Power (%)

"I Feel the Need, the Need for
Speed" (Clocking)

LVT

150

125

Cell: HD
Bits/BL: 32
Periphery: LVT
Area: 119.3%

Cell: HD
Bits/BL: 64
Periphery: LVT
Area: 100%

Power Too High
Cell: HD
Bits/BL: 64
Periphery: SVT
Area: 100%

Cell: HC
Bits/BL: 64
Periphery: SVT
Area: 118.6%
Cell: HD
Bits/BL: 32
Periphery: SVT
Area: 119.3%

100
Power Too
Low
75
90

95

100
105
Relative Performance (%)

110

115

FIGURE 8: An L1 SRAM's PPA tradeoff resulting in L1 CPU SRAM using HD with 32 bbl.

option tradeoff. LVT was eliminated
due to the impact of leakage power.
HD with 64 bbl does not meet perfor-
mance, so HD with 32 bbl or HC with
64 bbl is considered; compared to HD
64 bbl, these have +19.3%, and +18.6%
more area, respectively. As can be seen,
the HD 32 bbl has a 3% higher perfor-
mance and 9% lower power than the HC
64 bbl and, hence, is the topology used
for CPU L1 caches for optimal power,
performance, and area/cost [2].
Clock gating is a commonly used
methodology to reduce power. However,

clock-gating paths are frequently speed
bottlenecks in high-speed CPU imple-
mentations. A high-speed clock-gating
cell, shown in Figure 9, is devised to
replace the traditional clock-gating cells
(four inverter delays) in timing-critical
paths. The new cells offer data-to-output
timing of only two inverter delays [1].
One of the significant challenges
to logic performance in advanced
process technology pertains to the
midend-of-line (MEOL) and higher re-
sistance between transistors and in-
terconnects as the technology scales

IEEE SOLID-STATE CIRCUITS MAGAZINE

FA L L 2 0 17

31
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017
