IEEE Solid-State Circuits Magazine - Fall 2017 - 32

CK
VDD
TE

VDD

CK1

counterparts. Area impact from the
larger double-source cells is managed
by restricting their use to only the most
critical timing paths.

FF
FF
ECK FF

CK1

CK
TE

CK1

EN
ECK

CK1

ECK

CKN

CKN
VSS

VSS

High-Speed Clock Gating Cell

Traditional Clock Gating Cell

FIGURE 9: The EN to ECK critical path in the clock gate is optimized from four gates to two
gates. EN: enable; ECK: enable CK.

MEOL
Connections

FO4 Delay
(ps)

1
Xtor Source
5

Standard 2x INV

9.1

Double-Source 2x INV

8.6

Frequency Benefit

5.5%

FO4 Delay at 0.75 V, TT, 25 °C
Input

Output

1
4

FIGURE 10: A schematic and layout of a double-source inverter to reduce the MEOL resistance and improve speed.

to a smaller dimension [4]. To miti-
gate this impact, a new standard cell
topology was created in a 10-nm pro-
cess node. As shown in Figure 10, an
example topology of a 2× inverter, ad-
ditional transistors are placed to the
left and right of the active transistors
to reduce their source resistance. The
lowered source resistance and result-
ing performance benefit is achieved
by using an MEOL connection to short

FA L L 2 0 17

across the source and drain from the
source of the active transistors to the
respective power rail.
Since these additional transistors
have gate/drain/source shorted, they
do not add to device leakage or input
loading. This technique is applied to
inverters, buffers, and commonly used
combinational cells. The double-source
cells are over 5% faster and 18% lar -
ger on average than conventional

IEEE SOLID-STATE CIRCUITS MAGAZINE

Up the Food Chain (Circuit ➔
System ➔ Software ➔ Humanities?)
In any system the power/performan-
ce tradeoffs made at higher levels can
make or break any improvements
made at the lower levels. For exam-
ple, if many low-power knobs made
available at the circuit level are not
correctly used at the system or soft-
ware level, then the power overhead
at the higher level can not be opti-
mized away by circuit innovations.
Therefore cross optimizations from
circuits upward are vitally important
to the end product.
One such example is in the CPU
software model utilizing a heteroge-
neous multiprocessor (HMP) archi-
tecture. In mobile platforms, there
is a wide range of demand for high
performance in burst modes, sustain-
able performance in thermally limited
applications and low power modes
for continuous usage. Thus a hetero-
geneous multiprocessor architecture
that includes both high-performance
and low-power CPUs is adopted to fit
all the power/performance profiles
needed. Since this architecture is dif-
ferent than previous computing mod-
els of multiprocessor systems, a new
software model was needed. The ini-
tial models imposed a limitation where
only one CPU type can be active at a
time. For a truly heterogeneous expe-
rience, new HMP software allows the
application access to all of the proces-
sors in the asymmetric CPU subsystem
simultaneously. While inherently supe-
rior to the previous models, the HMP
performance remains highly depen-
dent on the quality of the heteroge-
neous scheduler embedded in the SoC
solution. An advanced scheduler algo-
rithm, combined with the asymmetric
CPU architecture and an adaptive
thermal and interactive power man-
agement system, maximize both per-
formance and energy efficiency [1].
An important input to the hetero-
geneous scheduler is the CPU power

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017