IEEE Solid-State Circuits Magazine - Fall 2017 - 43

sensitive registers (such as key reg-
isters) a re not included on sca n
chains or that these scan chains are
disconnected before shipment. For-
tunately, because cryptographic algo-
rithms aim at maximum confusion
and diffusion, fault coverage is typi-
cally very high for testing crypto-
graphic algorithms.

Gray Box Attacker Model:
The Present
Today, electronic devices and compu-
tations are more dispersed and distri-
buted. In the IoT context, we assume
that electronics are in the hands of
the user, e.g., mobile devices, smart
cards, game consoles, and other gad-
gets. Sensor nodes are distributed in
the environment, and medical devices
are implanted into our bodies. Elec-
tronics are everywhere in our cars:
to monitor sensors and drive actua-
tors, provide an entertainment sys-
tem, enable autonomous driving, and
more. Security, reliability, and safety
are of the utmost importance.
In this context, we assume an at-
tacker model in which the attacker
has access to both the communication
channel and the devices themselves,
as illustrated in Figure 2. Instead of
using only input/output plaintext/
ciphertext pairs, the attacker obtains
extra information by observing (a pas-
sive attack) or manipulating (an active
attack) one IC while it is performing
the calculations on the embedded
device. This extra side-channel infor-
mation can take many forms.

For typical digital circuit design, we distinguish
among the black box model (used mostly in the
past), the gray box model of current designs,
and the immersed model of the future.
Public key algorithms, such as RSA or
elliptic-curve public key schemes, typi-
cally scan the key bits in a bit-serial
fashion. A sequential implementation
that contains key-dependent if-then-
else structures will leak information:
when the if branch takes a different
execution time than the else branch,
the difference in execution time again
leaks information concerning the key.
Therefore, huge effort is spent to make
sure that a cryptographic implementa-
tion in hardware or software runs in
constant time.
For instance, it is crucial that finite-
state machines consume exactly the
same amount of cycles, independently
of the data being processed. Unfor-
tunately, most hardware optimiza-
tion and synthesis tools (and also
software compilers) will remove the
dummy code or logic that was added
to make a circuit or implementation
constant-time, because it is consid-
ered redundant or dead code. Hence,
there is a need for tools that check
or create constant-time implementa-
tions [7]. Note that timing attacks
can also be executed remotely; thus,
they are also a concern for cloud and
server implementations.

Side-Channel Attacks:
Simple and Differential
Similarly, data-dependent variations
in power consumption or electro-
magnetic (EM) radiation can reveal
sensitive data. Collectively, these
are called side- channel attacks.
These require that the attacker is in
close proximity to the device and can
monitor the power consumption or
pick up the EM radiation. Such attacks
are passive: they monitor the device
without disturbing its normal opera-
tion. The danger of passive attacks
is that the device itself might not
be aware that it is being monitored,
which is further evidence of the need
to develop circuits that can detect
observation [4].
Simple power attacks (SPAs) rely
on one or, perhaps, a few power or
EM measurements to obtain the secret
key. Template attacks are one exam-
ple of an SPA; here, a template of
the device under attack is available.
Creating the template could take a
huge number of measurements, but
the attack on the actual device might
take only one or, at most, a few such
measurements. (The term SPA is
somewhat misleading because, in

Timing Attacks
In a timing attack, the attacker will
observe differences in execution time,
depending on the values of the key or
other sensitive data. Cache attacks are
a well-known example. They are effec-
tive for table-based implementations
of the Sboxes of symmetric key algo-
rithms: if data in the cache depend on
the key, then timing differences leak
information [1].
In reaction, native AES instructions
were added to high-end x86 proces-
sors: these both improve performance
and run in data-independent time [10].

FIGURE 2: An example of the gray box attacker model, with the green dot representing the
device's root of trust.

IEEE SOLID-STATE CIRCUITS MAGAZINE

FA L L 2 0 17

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