IEEE Solid-State Circuits Magazine - Fall 2017 - 52

WLDAC
Code
WL
IBC

V1

MA

G1

MD

∆VBL
∆V

∆VBL(V)

0.06

I1 = V1 × G1

BLB

BL

V2

Ideal Transfer Curve
Standard Deviation
(from Monte Carlo
Simulations)

G2
I2 = V2 × G2

0.04
0.02
Nominal Transfer Curve
0

5

10

15 20 25
WLDAC Code

30

I = l1 + l2
= V1 × G1 + V2 × G2

35

(a) Multiplication Performed by
Bit Cell (Figure from [57])

(b) Gi Is Conductance of Resistive
Memory (Figure from [58])

FIGURE 7: Analog computation by (a) a SRAM bit-cell and (b) nonvolatile resistive memory.

increased speed or reduced energy
consumption. In Eyeriss [53], the PEs
are designed to skip reads and MACs
when the inputs are zero, resulting
in a 45% energy reduction. In [42],
specialized hardware is designed to
avoid computation and storage of zero-
valued weights, which reduces the
energy and storage cost by 43% and
34%, respectively.

Compression
L ight weight compression can be
ap plied to exploit data statistics
(e.g., sparsity) to further reduce data
movement and storage cost. Lossless
compression can reduce the trans-
fer of data on and off chip by around
2× as shown in [5], [44], and [55]. Lossy
compression such as vector quantiza-
tion can also be used on feature vec-
tors [42] and weights [3], [6], [56] such
that they can be stored on chip at low
cost. Note that when lossy compres-
sion is used, it is also important to
evaluate the impact on accuracy.

Opportunities in
Mixed-Signal Circuits
Mixed-signal circuit design can be
used to address the data movement

52

FA L L 2 0 17

between the memory and PE and also
the sensor and PE. However, circuit
nonidealities should be factored into
the algorithm design, for instance,
by reducing precision as discussed
in the "Opportunities in Joint Algo-
rithm and Hardware Design" section.
In addition, since the training often
occurs in the digital domain, the
analog-to-digital converter (ADC) and
the digital-to-analog converter (DAC)
overhead should also be accounted
for when evaluating the system.
While spatial architectures bring
the memory closer to the computa-
tion (i.e., into the PE), there have also
been efforts to integrate the compu-
tation into the memory itself. For
instance, in [57] the classification is
embedded in the SRAM [Figure 7(a)],
where the bit-cell current is effec-
tively a product of the value of the
5-b feature vector (WLDAC) that
drives the word line (WL), and the
value of the binary weight stored
in the bit cell. The currents from
bit cells in the column are added
together to discharge the bit line
(BL) by TVBL. This approach gives
12× energy savings over reading the
1-b weights from the SRAM.

IEEE SOLID-STATE CIRCUITS MAGAZINE

Recent work has also explored
the use of mixed-signal circuits to
reduce the computation cost of the
MAC. It was shown in [59] that per-
forming the MAC using switched
capacitors can potentially be more
energy efficient than digital circuits
at low bit widths despite ADC and
DAC overhead. In [60] and [61], the
matrix multiplication (with bit widths
less than or equal to 8 bits) is inte-
grated into the ADC; this also moves
the computation closer to the sensor
and reduces the number of ADC con-
versions by 21×.
To further reduce the data move-
ment from the sensor, [62] proposed
performing the entire CONV layer
in the analog domain at the sensor.
Similarly, in [63], the entire HOG
feature is computed in the analog
domain to reduce the sensor band-
width by 96.5%.

Opportunities in
Advanced Technologies
Advanced technologies can also be
used to reduce data movement by
moving the processing and mem-
ory closer together. For instance,
embedded DRAM (eDRAM) and hyper
memory cube (HMC) are explored
in [39] and [64], respectively, to
reduce the energy access cost of the
weights in DNNs. The multiplication
can also be directly integrated into
advanced nonvolatile memories [65]
by using them as resistive elements
[Figure  7(b)]. Specifically, the multi-
plications are performed where the
conductance is the weight, the volt-
age is the input, and the current is the
output; the addition is done by sum-
ming the current using Kirchhoff's
current law. Similar to the mixed-sig-
nal circuits, the precision is limited,
and the ADC and DAC overhead must
be considered in the overall cost.
DNN processing using memristors is
demonstrated in [58] and [66], where
the bit width of the memristors is
restricted to between 2 to 4 bits.
The computation can also be em -
bedded into the sensors. For instance,
an angle sensitive pixels sensor can
be used to compute the gradient of



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