IEEE Solid-State Circuits Magazine - Fall 2017 - 61

In the systolic processing concept, a 2-D array
of functional units processes data locally and
passes inputs and intermediate results from
unit to unit instead of to/from global memory.
in [14]) or even just registers (as in [9])
to store data locally and maximize
data reuse within the array. Processing happens as a systolic wavefront
through the array, wherein weight
coefficients can be kept stationary in
the functional units, input data are
shifted in one direction through the
array, and output data accumulate in
the orthogonal direction. This allows
the performance of a very large number of computations for convolution
or matrix multiplication in parallel
by keeping all systolic elements busy
without burdening the memory bandwidth. Interested readers are pointed
to [15] and [9] for more details.
Such systolic operation opens the
door to in-memory computing, where
the computation is integrated inside
the memory array. While this is also
pursued in traditional memory architectures, the results look especially
promising for emerging nonvolatile
memory arrays. For example, in resistive
memory technologies, a multiplication
can be implemented by exploiting
the memory cell's conductance as the
kernel weight, while accumulating current from different elements to implement the convolution's accumulation
operation [16]. However, this technology currently still suffers from large
variability, limiting applications to very

low-resolution operations with very limited kernel and network sizes.
While all the aforementioned techniques can dramatically boost the
system's throughput and energy efficiency, it is important to keep an eye
on their impact on the design's programmability and flexibility. Especially in the fast-paced area of deep
learning, it is of the utmost importance to maintain sufficient flexibility
toward alternative network dimensions
and novel network topologies. Most
accelerators, however, succeed in this
by enabling the acceleration of matrix
multiplications (for the fully connected layers) and convolutions (for
the convolution layers) of any size,
yet with maximal efficiency for a subset of sizes.

Enhancing and Exploiting
Fault Tolerance
A second important aspect of deep
neural networks that can be exploited
in custom processor designs is their
fault tolerance. Many studies observe
the robustness of CNNs and other
networks to perturbations on their
weight parameters and intermediate
computational results [17], [18]. This
can be exploited both at the hardware as well as the algorithmic level
in several ways.

MAC Array
On-Chip
SRAM

Off-Chip
DRAM

MB
Tens of pJ/Word

GB
Hundreds of pJ/Word

Local
SRAM
kB
pJ/Word

Registers

the network itself. A more elaborate
overview of the different parallelization schemes can be found in [11]
and [12], along with an assessment of
their merits.
A complementary way to reduce
the energy burden of continuous
data fetches is not to minimize the
number of data fetches but rather to
reduce the energy cost of every data
fetch by exploiting temporal data
locality. Most realistic deep networks
require so much weight and input/output memory (megabytes to gigabytes)
that it is impossible to fit them in on
a chip memory, thus requiring fetches
from energy-costly external dynamic
random-access memory (DRAM). Similar to traditional processors, this can,
however, be mitigated by a memory
hierarchy having one or more levels of
on-chip static RAM (SRAM) or register
files. Frequently accessed data can, as
such, be stored locally to reduce its
fetching cost (Figure 9).
An important difference with general-purpose solutions, however, is
that the sizes of the memories in the
hierarchy can be optimized toward
the network's structure, e.g., foreseeing a local memory capable of caching exactly one weight tensor, or one
of the tensor [11]. Even more importantly, the networks can be trained
with the processor's memory hierarchy in mind. As such, networks have,
e.g., been explicitly trained to completely fit in on-chip memory. This
optimization is, of course, highly
interwoven with the parallelization
scheme. By jointly optimizing these,
one can adjust the degree of parallelization to the memory hierarchy and
minimize the product of the number
of memory accesses with the cost of
every memory access [13].
Distributed and systolic processing can be seen as an extreme type
of such hierarchical memories. In the
systolic processing concept, a 2-D
array of functional units processes
data locally and passes inputs and
intermediate results from unit to
unit instead of to/from global memory. These functional units are each
equipped with a very small SRAM (as

B




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