IEEE Solid-State Circuits Magazine - Fall 2017 - 74

In this second part, we will investigate how
this simplified EKV model can be used to
explore the various tradeoffs faced when
designing analog circuits.
linearity, gain, supply voltage, voltage swing, speed and input/output
impedance, as illustrated by Razavi's
analog design octagon, shown in Figure 1 [1]. After having found the most
appropriate system architecture and
circuit, the designer finally needs to
select the right drain bias current,
channel width, and length for each
metal-oxide-semiconductor (MOS)
transistor [2]. These three independent degrees of freedom for each
device influence their performance,
including bias voltages, dc gain, bandwidth, noise, matching, and linearity and hence have an impact on the
overall circuit performance [2].
Among all the transistor parameters (current, width, length, and bias

voltages), the overdrive voltage VG - VT0
has been used as a key design variable for a long time. However, with
the down-scaling of complementary
MOS (CMOS) technology, the operating points of MOS transistors have
been progressively pushed toward
moderate or even WI (subthreshold
region), where the overdrive voltage
is not convenient anymore. To cover
the whole range of operating regimes
from WI to SI, we propose replacing the overdrive voltage by the IC
describing the state of inversion of
the channel from weak via moderate
to SI.
The concept of IC was introduced in
the first part of this article [3], together
with the simplified charge-based

Linearity

Noise

Power

Basic Tradeoffs in Analog IC Design
Gain

Supply Voltage

I/O Impedance

Voltage Swing

Speed

FIGURE 1: Razavi's analog design octagon, illustrating the tradeoffs faced in the design of
analog circuits [1].

W/L

W/L
Vout

Vin
(a)

Vin

W/L
Vout

W ⋅CW CL0

Vin

(b)

Vout

(c)

FIGURE 2: CS gain stage schematics for the calculation of (a) constant G m, (b) constant GBW,
and (c) constant GBW including self-loading.

FA L L 2 0 17

IEEE SOLID-STATE CIRCUITS MAGAZINE

Enz-Krummenacher-Vittoz (EKV) M O S
field-effect transistor (FET) model
that can be used to model devices in
saturation even in advanced CMOS
processes with only a few parameters including the effect of VS. The
model includes simple expressions
of the normalized (source) transconductance and the transconductance
efficiency G m /I D in terms of IC and
the VS parameter m c . Similarly, the
output conductance in saturation for
short-channel devices can also be
ex pressed in terms of IC and two
additional parameters m d and v d .
The model was validated on several
advanced bulk and fully depleted
silicon on insulator (FDSOI) CMOS
processes [3].
In this second part, we will investigate how this simplified EKV model
can be used to explore the various
tradeoffs faced when designing analog circuits. Since much circuit performance directly depends on G m
and/or G ds, it can be characterized
over a wide range of bias using the
expressions of G m and G ds.

The transconductance, and hence
the current and area, of a singlestage amplifier or a differential pair
is often dictated by the requirements on gain, GBW product, and
noise [4], [5]. Because the transconductance is proportional to the aspect
ratio W/L and increases with the
current, the same transconductance
can be achieved for different W/L
ratios and bias current. Hence, the
designer still has the degree of freedom to choose the appropriate IC at
which the device needs to be biased
to achieve a given transconductance.
It will be shown below that moving the operating point to MI or WI
actually comes with a reduction of
current at the cost of an increase in
area to achieve the same transconductance, GBW, or input-referred
thermal noise [4], [5]. To show this,
we will look at the simple CS stage
shown in Figure 2. We will investigate how the bias current I b and
a sp e c t r a t io W/L of a transistor

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2017